## Background

As part of a to-be-announced project I am working on, I ended up designing a new Toshiba TB6621FNG motor control board which is designed to be compatible with the Raspberry Pi. Before I began this design, the lab I am working in had been using controllers based on the Rohm BD6222HFP chip. This is a chip which is well suited to hefty 12V designs. However, we now need something more efficient and less expensive. The TB6612FNG chip is:

• Less expensive (by ~\$1 at single unit scale)
• Requires more hobbyist friendly supply voltages ( 3-5.5V instead of 6-18V)
• Provides similar output amperage compared to the Rohm chip.
• Input current in standby (IIH) averages 35μA less.

All this lead me to design around the new chip. Of course, breakouts from the usual suspects such as Sparkfun (seen here) and Adafruit (seen here) are available. Adafruit even provides an advanced version which is (in my opinion) over-specialized (see it here). So why did I reinvent the wheel in this case? Because the basic breakout boards are too limited and the advanced version is too limiting.

## Pi Woes

The GPIO pins on the Raspberry Pi are a wonderful thing. They provide so much room for innovation. However, when you only need one or two specific pins, and those pins are scattered all over the GPIO, it is inconvenient and slightly expensive to design a board with the full 26 pin socket. Instead, selective use of 3-pin servo headers can be used at lower cost. The TB6612FNG motor control board I designed uses this type of design.

Additionally, there is a problem unique to certain pins of our good ol’ GPIO friend. During boot, pins are not consistently pulled up or down. This can mean that a motor run by these pins may do strange things during boot. If one of those motors is controlling some sort expensive optics as in my case, this is to be avoided. There are a few work around options for this. It is possible to set up a cron job at boot which will set all of the pins to pull up or down, but this may be a challenge to a user with less bash experience. For my project, I need something that allows a user to run the device without worrying about the details. So I implemented a hardware solution. The GPIO pins are pulled down by 100k resistors on my TB6612FNG motor control board.

An advanced setting was made available to divorce the chip ground from the motor power ground by way of a solder jumper.

## Schematics

Pictured below is the schematic for my TB6612FNG motor control board. The project was designed with KiCAD.

The picture below shows the layout of the board, omitting the back copper plane. I was able to fit all of the traces on one side of the board, so the B.Cu layer is mostly ground plane thermal relief.

Next week, I will show how I made the board.

## SiC Logic: A Rejected Proposal

This is a proposal I wrote and submitted to the July 2017 cycle of the NASA NPP program to work on development of SiC logic for a Venusian satellite project.. It was rejected and I went another direction. The SiC logic proposal idea was generally well received. While many of the reviewers comments could have been addressed in a treatise with ample page limits, there was little I could do about the primary concern. It is clear that the reviewers would have been more comfortable awarding the postdoctoral position to someone who had worked with silicon carbide before, rather than explaining in theory and going for on-the-job experience. This is a fair assessment that I suspect I will never be able to address, as SiC logic is not a common enough field to get easy exposure too.

So with the understanding that I will likely not be able to work on this in the future, I would like someone else to pick up the reins and move forward with the project. This is a very important project that has many applications, as will be addressed below. I urge readers to STEAL THIS WORK. Therefore, I am taking the time to release this rejected proposal on my site to allow others to learn from it and, hopefully, continue the proposed project. The full text of the project is below, modified from the original to fit the current medium.

As always, feel free to contact me for info or to chat about this.  My contact info can be found on the CV page.

# Development of Logical Circuitry using Silicon Carbide Substrates for Control Circuits in Harsh Environments

by

## 1. Statement of problem

Recently, NASA has begun prioritizing an exploratory mission to Venus [1], including a surface lander [2]. Previous landers from the Venera program by the USSR were only able to last, at most, two hours on the unforgiving Venusian surface [3]. The extreme temperatures and oxidative atmosphere of the planet’s surface mean it is very difficult for current electronic systems to perform for extended periods. While a wealth of new high temperature and pressure sensing instruments have been developed as part of the Venus Exploration Analysis Group (VEXAG), the glue electronics to control and operate such a lander are still elusive [4].
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The development of silicon carbide (SiC) semiconductor devices has gained increasing popularity in the past 20 years, yet the technology lacks the wide breadth of available devices which competing substrates currently offer. Far from the first light emitting diode [5] [6] which was originally made in SiC, today SiC can be found in many high power applications. Recent developments have even allowed the creation of power switching devices with high-voltage junction temperature tolerance up to 1200 V in both JFET and MOSFET designs [7] [8]. Current SiC logical devices are produced using JFET technology. Core logic gates such as the inverter, NAND, and NOR have been demonstrated in both depletion mode [9] and enhancement mode [10] SiC JFET. Despite recent demonstrations of a ring oscillator and development of 100’s scale transistor level logic using SiC JFET technology [11], there is a dearth of advanced logic designs for SiC circuits which would further the NASA Venus lander objectives. The goal of this proposed work is to develop discrete digital logic devices using SiC substrates and patterning.

## 2. Background and relevance to previous work

Silicon carbide has several interesting properties that make it an attractive semiconductor platform for devices intended to withstand harsh environments. At standard atmospheric pressures, SiC remains crystalline with no defects at temperatures up to 2760 °C before partial sublimation [12]. At higher pressures, this temperature stability increases. Under 100 atm, similar to the pressure at the surface of Venus, SiC remains solid up to 2830 °C before melting. Individual junctions of p-doped and n-doped SiC material have a much higher tolerance for heat than more commonly used substrates such as Si. This is because the optimum working temperature of SiC is very close to the highest normal mode vibrational temperature, or band gap [13]. Microelectromechanical systems (MEMS) based on SiC have been established as a viable device for some time [14], and some developed MEMS devices are pushing temperature limits in sensors [15]. Logic gates manufactured from SiC can take advantage of this property by creating devices which tolerate high voltage switching, a task which produces a large amount of heat [16]. The converse can be true as well: it is possible to make low power logic gates that tolerate extreme temperatures.

Additionally, SiC has been shown to be particularly resilient against radiation damage. Circuits made of SiC have been reported to exhibit much lower rates of carrier damage due to deep material defects caused by neutron flux, with McGarrity et al. reporting 1/3 of the damage compared to Si based devices at doses of 1016 neutrons/cm2 [17]. This makes SiC technology attractive for radiation heavy environments, including satellites and exploratory vehicles. The large gate sizes in current SiC technology compared to modern CMOS feature sizes makes the SiC further resistant to radiation effects [18]. If this material is used for the sensitive electronic equipment, it is possible to have reduced failure rates with current design specifications. Furthermore, it is possible that future devices using this technology may require less device redundancy for radiation hardening purposes, making it possible to create exploratory vehicles with greater computational power and reduced power consumption.

Logical units for SiC are designed by the NASA Silicon Carbide Electronics and Sensors group using depletion mode JFET technology on both 4H-SiC and 6H-SiC wafers. At the simplest level of description, an n-type JFET, the most durable and stable type for high temperature operation [11], is a transistor gate with the drain and source connected to an n-type substrate with a p-type gate separated by a depletion layer. A detailed diagram of the current archetypal SiC JFET layers can be found in the literature [19]. These JFETs are normally ON devices which switch OFF when a voltage applied to the gate passes a certain threshold in a reverse biased regime. Due to this design, the source requires a negative voltage, making the HIGH and LOW bits ground and a negative voltage, respectively. As certain parts of a logical array require a positive voltage, a JFET logic circuit is necessarily more complex to design due to the presence of an additional power rail. Further complications arise from the body bias effect based on the substrate voltage [20] and radially dependent resistivity observed in printed wafers [19].

As a physical chemist, I have an outside perspective on device function at the gate interface level which allows for a critical approach to the challenges posed by innovative logic design. My previous experience with silicon based control systems has demonstrated that I am capable at computer aided design (CAD) of electronic systems [21]. In addition to my design experience, I have also used modeling programs such as SPICE to characterize the behavior of a Fourier transform device for monitoring sample conductivity. Modern developments in microcontroller prototyping boards allow for integration of one device to test another. My previous work gave me experience with prototype evaluation of electronic systems and bringing a scientific approach to an engineering problem. Particularly, previous designs for sensors deployed in unpredictable climates have made me conscious of the need for devices built to tolerate these conditions including temperature dependent conductivity sensors [22]. As a scientist who enjoys developing devices for monitoring and evaluating physical and chemical properties, the challenges posed by SiC JFET design appeal to my desire to broaden my skills.

## 3. General methodology, procedures to be followed, and timeline for completion of each step

The goal of this proposed work is to develop logic circuits required for a low power monitoring device tolerant to harsh conditions by application of known computing architecture to the emerging silicon carbide technology. At the highest level of abstraction, a device of this nature requires a central processing unit (CPU), level shifters, analog to digital converters (ADC), switched power supply units (PSU), and memory. Certain portions of this list, including level shifters [9], ADC [23], and PSU [24], have been demonstrated in previous research. In the case of a modern application, a single package microprocessor can handle most of these tasks. However, minimal work has been done creating complex logic for the CPU in SiC. The development of this device must start from a basic level, designing the subcomponents of the CPU individually.

A CPU can be generalized as a combination of individual logic units, primarily these are registers and arithmetic logic units (ALU). The goal of this proposal is to develop the technology in SiC JFET for both of these logic units to create a functional 8-bit microprocessor.

### 3.1 Register

##### Figure 1

###### This is an example register design showing the design hierarchy. Part 𝒶 shows the primary user accessible 8-bit registers included in the design of the popular Intel 8085 chip [25]. Part 𝒷 shows detail of one register from part 𝒶 [26] [27]. Each bit of the register is a flip-flop which adjusts the value from D to Q for each bit on in a clock cycle. Part 𝒸 shows one of these flip-flops. A flip-flop is composed of two latches, a master and a slave, which copy D to Q on the rising edge of the clock cycle. This saves the state of the flip-flop at all other times. Part 𝒹 shows one of the latches, a simple logic circuit consisting of one NOT, two ANDs, and two NORs in a bistable arrangement. Part ℯ shows a diagram of one CMOS NOR gate depicted in part 𝒹 as they would be designed for patterning on the SiC surface using the program MAGIC [28]. In short: multiple of ℯ make up 𝒹, which make up 𝒸, which make up 𝒷, which make up 𝒶.

The register is a logic unit which is included in many important CPU and device components such as the primary register, memory, instruction set, and program counter. To construct this unit, we must reduce this piece down to its relatively simpler components. The register is a series of clock synchronized flip-flops, a flip-flop is a pair of latches, a latch is simply a pair of NOR gates connected in a certain manner, and a NOR gate is constructed from a few individual transistors. Figure 1 shows the decreasing levels of abstraction from the register of a popular integrated circuit to the layers and doping of a single NOR gate designed for CMOS technology. The transistor technology for JFET SiC gates have been previously demonstrated for NOR gates, making the technology scale up possible.

Due to the synchronous nature of the register and the importance of timing in computing, each device will be rigorously analyzed as it is created and tested. As it is impractical to directly measure single gate delay, a value which is often on the scale of picoseconds, it is useful to estimate the rise and fall of a signal through a gate using computational models and values of capacitance and current for each interconnect [29]. The delay for multiple equivalent gates is additive at scale, making the averaged delay over multiple gates in a device a calculable quantity with simple instrumentation. The averaged gate speed can be measured by construction of an array of latches acting asynchronously. This will be used to verify computationally calculated values.

Keeping with the “bottom-up” approach to design on the SiC substrate, the first task will be designing and verifying a single bit flip-flop, which has not been reported in literature. The patterned device will be characterized by tests to determine the ability to retain and replace the bit over multiple clock cycles. As SiC devices are being sought to operate in harsh conditions, tests will be undertaken to determine the bit retention ability of the flip-flop at a range of temperatures from standard conditions to >500 °C. Testing of the device can take place with a voltage monitor (capable of determining bit state) at short time scales and a local RC oscillator (as oscillators must be close to the circuit to prevent return current, making an external crystal oscillator impractical for high temperature tests). The second task will be to scale this device up to a full 8-bit register. Findings from the first task will be used to determine the design of this circuit, and it will be tested and verified in a similar manner.

### 3.2 Arithmetic Logic Unit

Another essential component of the CPU is the Arithmetic Logic Unit (ALU). This is an umbrella term for portion of the processor which performs simple arithmetic operations such as addition, subtraction, multiplication, division, and comparison. Each of these operations requires a distinct circuit. The addition and subtraction circuitry will be designed in the form of a carry-lookahead adder (chosen for the ability to perform faster calculations than many other adder circuits, a property which will be valuable in lifetime-limited missions), using two’s compliment values for subtraction operations. The multiplication and division operations will be performed on circuitry designed using logical and arithmetic shifters. Equality comparators are simple ANDs of a number of XNOR gates, which can be constructed from the NAND and NOR gates available in SiC JFET. Magnitude comparators are a variant of subtractors. All of these have well documented logical designs which can be applied to SiC systems.

Simple arithmetic circuits are used throughout the computer system. For example, operations are performed based on orders delivered by Operation Codes (Opcodes) from the program register. These instructions must be interpreted by the logic of the device by arithmetic means. For example, an adder is used to determine the address of the next instruction from the program counter, and a control ALU is utilized to compute the memory address of data to be operated upon by the CPU. With a working register established, it will be necessary to develop a way to utilize the register directly by furnishing it with operations. The development goal of designing a working ALU furthers the overarching goal of creating a working processor, as the individual components of the ALU are used in many places.

The first task of the ALU portion of this proposal is to demonstrate a simple half-adder circuit patterned in SiC. The half-adder will be fed alternating values of HIGH and LOW on both inputs to determine if a correct value is generated for the output and/or the carry of the circuit. The input for this circuit will be generated by an external microcontroller such as an Arduino prototyping board timed to send the signal pulses at regular intervals and check the answers. The Arduino will log the inputs, output, and carry from this circuit to check for errors. This experiment will be repeated in both standard conditions and harsh conditions in excess of 500 °C to simulate real operation. The Si based Arduino signal generation and logging can be isolated from the elevated temperature conditions since HIGH and LOW signals are not subject to the same trace length constraints as oscillators. Success of the circuit will be determined by continuous operation without errors with a lifetime to match previously explored logical units [30], discussed further in Section 5. The next task will be to scale up to an 8-bit full adder, then to a carry-lookahead adder which will be tested in the same manner.

Comparators and shifters will be tested in a similar “bottom-up” manner and constraints as the adder. For the comparator, initial tests will be performed on a simple 2-bit comparator, then scaled up to a full 8-bit comparator. The first bit shifter will be a simple array shifter of 2-bits, tested by cycling the bit shift by one unit over time. The scaled up version of the shifter will be tasked with performing full 8-bit shift operations. Tests will be performed at a range of temperature conditions and deemed successful for continuous operation without errors, similar to the other proposed units of the ALU.

## 4. Explanation of new or unusual techniques

The proposed work is unique in that it uses SiC for logical device fabrication. There are very few devices which use this technology, and use of substrate materials outside of Si in CMOS design is uncommon due to industry focus on small feature sizes and high computational power. While this is a new and exciting area of research, there will be few novel techniques implemented at this stage. The design flow for computers at the Si level is so well documented that many university level research institutions offer courses on the most up-to-date processes available. However, the technology for SiC devices is young compared to Si devices, many of these modern methods make use of architecture and design technology not prepared for the simplicity of SiC. Therefore, a “back-to-basics” approach is more suitable for this project. The “back-to-basics” approach will favor the use of the original VLSI work pioneered by Mead and Conway, and their contemporaries [31] [32] [33].

While much of the design for modern integrated circuits is handled by computational algorithms, few such mathematical models are available for the SiC substrate. The current state of circuit simulation makes use of NMOS SPICE models with certain parameters ignored [11]. Instead, a more traditional approach to device design must be considered. Masks for experimental devices will require manual generation based on traditional standard for VLSI device production pioneered by Mead and Conway [31]. Previous work by the SiC group at NASA has produced some important values for device modeling including size constraints. Physical constants observed in this work will be used to further develop a custom technology profile for SiC in a VLSI design program such as MAGIC [28]. By recording these parameters, it is possible to approach the algorithmic simplicity enjoyed by traditional substrate devices, establishing Electronic Design Automation (EDA). The modularity and regularity inherent to the nature of computer design makes these values extremely valuable as the overarching project scales up. Furthermore, VLSI EDA programs can be used in conjunction with SPICE to simulate the designed circuits at the pattern level [34].

## 5. Expected results and their significance and application

The qualifications for an individual circuit success were previously mentioned in Section 3. Generally, these success criteria can be divided into data retention time for register devices and continuous error-free operation time for ALU related devices. Some electronic properties are temperature dependent, such as resistance [19] and band-gap [35]. Therefore, it is critical to test circuits designed for optimal operation at one temperature over the range of possible operations temperatures. These tests are to be replicated at both standard temperatures and temperatures found in harsh conditions, such as the surface of Venus, using lab ovens.

A successful register is a device which can retain the stored data over many clock cycles, and change each bit in a timely manner on the rising edge of a single clock cycle. To determine the size of this clock cycle, we look to a reference point, such as a previous lander. The Sojourner Rover utilized a variant of the Intel 8085 chip, the 80C85, running at a clock speed of 2 MHz} [36]. The manufacturer reported maximum clock speed of this CPU is 5 MHz} [37]. Therefore, for the purposes of this test, the success factor will assuming an acceptable operation speed of 2 MHz} with an optimum operation speed of 5 MHz}. If we assume that the bit stored in the flip-flop is either modified on each clock cycle or stored for the clock cycle, and we assume that the chance for a bit to be either 0 or 1 is equal, then we can be 99% confident the longest a bit will be stored in a single flip-flop is 7 clock cycles. Therefore, the produced register will be adequately successful if it can retain a bit for 350 ns and exceed success if it can retain a bit for 1.4 μs.

A successful ALU is a device which can perform the requested operation quickly, with no errors. In a surface level lab with minimal radioactive sources, it should be expected that an adder or bit shifter would work consistently. However, no device is perfect, and chip manufacturers are hesitant to publish failure rates in their devices. Certain failure modes, such as electromigration, are tested for using temperature acceleration. However, the original draw of SiC circuits is the high temperature stability, reducing the likelihood of this failure path [38]. With the lack of benchmarks for ALU failure and the high temperature stability expectation which can accelerate further testing, the success metric will be based on the previous performance reported by the Hunter group, including a thousand hour lifetime of an oscillator at 500 °C [30]. The ALU produced in the course of the work in this proposal will be considered a success if the error-free lifetime exceeds 1000 h, the time reported by Spry et al.

In the event the devices fail to pass benchmarks for the register, ALU, or their preceding variants, efforts will be made to determine the cause of the issue. Previous circuit issues which have been a cause of concern in the past, such as the micropipe defects in SiC devices [38], have been analyzed in detail [39] based on “failed” experiments. This provides much needed data for future improvements on the material. Circuits which do not meet benchmark expectations will be analyzed by electron microscopic techniques for sources of damage, much like the previously mentioned failure was determined to be due to oxide cracking in the thousand hour test [30]. These sources of failure can provide more evidence to shed light on the cause of such defects in SiC systems.

The technology developed for this work has far-reaching applications. There have been few complicated logic devices made in SiC [30]. A successful register and ALU would open the doors to further development in this material, eventually leading to the eventual development of a single-cycle microprocessor CPU with high temperature and radiation resistance. Processors in this material would be very attractive for future space-faring missions and use in extreme terrestrial environments. The individual building blocks produced by this work can also be used as a basis for other SiC devices. For example, the development of a successful 8-bit register would naturally lead to the development of ROM and RAM with similar configurations. The modularity and repeatability of these devices makes it relatively simple to drop a successful gate design from one project to the next. By designing these devices in a prevalent, open-source VLSI EDA environment, the parameters explored in these designs would be available to future designers working with this technology.

## 6. References/Citations

[1] R Herrick, K Baines, M Bullock, G Chin, B Grimm, W Kiefer, S Mackwell, K McGouldrick, B Sharpton, S Smerkar, and others. Goals Objectives and Investigations for Venus Exploration. Venus Exploration Analysis Group (VEXAG), 2014.

[2] T Kremic, GW Hunter, PG Neudeck, DJ Spry, GE Ponchak, GM Beheim, RS Okijie, MC Scardelletti, JD Wrbanek, DM Vento, and others. Long-Life In-Situ Solar System Explorer (LLISSE) Probe Concept and Enabling High Temperature Electronics. In Lunar and Planetary Science Conference, volume 48, 2017.

[3] Donald M Hunten. Venus. University of Arizona Press, 1983.

[4] Jeff Balcerski. Venus Science Priorities for Laboratory Measurements and Instrument Definition Workshop Report. Technical report, National Institute of Aerospace, Langley, VA, April 2015.

[5] H. J. Round. A Note on Carborundum. Electrical World, 49(6):309, February 1907.

[6] O. V. Losev. Luminous carborundum detector and detection with crystals. Telegrafiya i Telefoniya bez Provodov, 44, 1927.

[7] R. Siemieniec and U. Kirchner. The 1200V direct-driven SiC JFET power switch. In Proceedings of the 2011 14th European Conference on Power Electronics and Applications, pages 1–10, August 2011.

[8] K. Mino, S. Herold, and J. W. Kolar. A gate drive circuit for silicon carbide JFET. In Industrial Electronics Society, 2003. IECON ’03. The 29th Annual Conference of the IEEE, volume 2, pages 1162–1166 Vol.2, November 2003.

[9] M.J. Krasowski. N Channel JFET Based Digital Logic Gate Structure. Google Patents, March 2010.

[10] H. Habib, N.G. Wright, and A.B. Horsfall. Complementary JFET Logic for Low-Power Applications in Extreme Environments. In Silicon Carbide and Related Materials 2012, volume 740 of Materials Science Forum, pages 1052–1055. Trans Tech Publications, March 2013.

[11] Phillip G. Neudeck, David J. Spry, and Liangyu Chen. First-Order SPICE Modeling of Extreme-Temperature 4H-SiC JFET Integrated Circuits, May 2016.

[12] Vera Haase, Gerhard Kirschstein, Hildegard List, Sigrid Ruprecht, Raymond Sangster, Friedrich Schröder, Wolfgang Töpper, Hans Vanecek, Werner Heit, Jürgen Schlichting, and Hartmut Katscher. The Si-C Phase Diagram. In Vera Haase, Gerhard Kirschstein, Hildegard List, Sigrid Ruprecht, Raymond Sangster, Friedrich Schröder, Wolfgang Töpper, Hans Vanecek, Werner Heit, Jürgen Schlichting, Hartmut Katscher, Raymond Sangster,
and Friedrich Schröder, editors, Si Silicon: System Si-C. SiC: Natural Occurrence. Preparation and Manufacturing Chemistry. Special Forms. Manufacture. Electrochemical Properties. Chemical Reactions. Applications. Ternary and Higher Systems with Si and C, pages 1–5. Springer Berlin Heidelberg, Berlin, Heidelberg, 1985.

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[21] Wesley T. Honeycutt. Development and Applications of Chemical Sensors for the Detection of Atmospheric Carbon Dioxide and Methane. Dissertation, Oklahoma State University, Stillwater, Oklahoma, May 2017.

[22] Wesley T. Honeycutt, M. Tyler Ley, and Nicholas F. Materer. A Comparison of the Properties of Selected Commercially Available, Low-cost Carbon Dioxide and Methane Gas Concentration Sensors. Sensors Journal IEEE, 2017 [Submitted].

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[24] Saleh Kargarrazi, Luigia Lanni, Stefano Saggini, Ana Rusu, and Carl-Mikael Zetterling. 500◦ C bipolar SiC linear voltage regulator. IEEE Transactions on Electron Devices, 62(6):1953–1957, 2015.

[25] Intel Corporation. 8080/8085 Assembly Language Programming Manual. Intel Corporation, Santa Clara, 1978.

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[30] David J Spry, Philip G Neudeck, Liang-Yu Chen, Dorothy Lukco, Carl W Chang, Glenn M Beheim, Michael J Krasowski, and Norman F Prokop. Processing and characterization of thousand-hour 500◦ C durable 4H-SiC JFET integrated circuits. Additional Papers and Presentations, 2016(HiTEC):000249–000256, 2016.

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## LaTeX: Drawing MOSFET in TikZ

I’m a big fan of using LaTeX for my scientific writing.  (What is LaTeX? It is a typesetting programming language that gives you much more flexibility than other writing environments.  wikipedia)  Since I have some time on my hands, I wanted to prepare for future presentations by writing up some notes and slides using in LaTeX for future use.  This includes drawing diagrams using TikZ.  This post describes how to draw a simple, generalized MOSFET in TikZ while standardizing some of the layer notation.

## Setting up the Beamer environment

Before we get started with our drawing, let’s first set up a simple LaTeX environment.  Let’s say we want to make some slides for a lecture.  We can use the Beamer class in LaTeX to make these slides.  We tell LaTeX what we what to do.

\documentclass{beamer}

\begin{document}

\end{document}


Now, we add some title information into the preamble of the code, and we tell the document to produce a title slide.

\documentclass{beamer}

\title{Dr. Honeycutt's \LaTeX Surface Science and Electronics}
\author{Wesley T. Honeycutt}
\date{\today}

\begin{document}

\frame{\titlepage}

\end{document}


The “\frame” command tells the LaTeX compiler to produce a single slide with the content in the curly braces. For our title slide, we want the content to be the information title information we included in the preamble. After compiling, it should look like this:

If you want to make your slides look fancy, there are plenty of things you can do. For this demonstration, we are only need a simple framework for the TikZ drawing, so we will just leave it at the default.

## Drawing the MOSFET in TikZ

Now we are going to make a new slide with our drawing. We tell LaTeX that we will be using TikZ in the preamble. Then, we start a new slide (“\frame”) and begin our drawing. If you don’t know what a MOSFET is, or you just need a bit of a refresher, check out this for reference. Here is what my code looks like:

\documentclass{beamer}

\usepackage{tikz}

\title{\LaTeX~Surface Science and Electronics}
\author{Wesley T. Honeycutt}
\date{\today}

\begin{document}

\frame{\titlepage}

\frame{\frametitle{MOSFET}
% General n-type mosfet
\begin{tikzpicture}
\draw (0,.25) -- (0,3) -- (1,3) -- (1,2.5) to [out=270,in=180] (1.5,2) -- (3.75,2) to [out=0,in=270] (4.25,2.5) -- (4.25,3) -- (6.75,3) -- (6.75,2.5) to [out=270,in=180] (7.25,2) -- (9.5,2) to [out=0,in=270] (10,2.5) -- (10,3) -- (11,3) -- (11,.25) -- (0,.25);
\draw (0,0) rectangle (11,.25);
\draw (4,3) rectangle (7,4);
\draw (4,4) rectangle (7,4.5);
\draw (4.25,3) -- (1,3) -- (1,2.5) to [out=270,in=180] (1.5,2) -- (3.75,2) to [out=0,in=270] (4.25,2.5) -- (4.25,3);
\draw (10,3) -- (6.75,3) -- (6.75,2.5) to [out=270,in=180] (7.25,2) -- (9.5,2) to [out=0,in=270] (10,2.5) -- (10,3);
\draw (1.25,3) rectangle (3,3.5);
\draw (8,3) rectangle (9.75,3.5);
\end{tikzpicture}
}

\end{document}


In the preamble, I have told LaTeX I will be using the TikZ package. After the title slide, I added a new “\frame” and gave it a “\frametitle”. Note how the curly brace of the “\frame” does not close until line 25. In this “\frame” I have started a tikzpicture environment. This tells LaTeX that it should start using the TikZ code in this section. I have two types of drawings here. The first are simple rectangles. These rectangles are bounded by the opposing corners in (x,y) coordinates. The default units here are cm. The second type of drawing is a complex line shape. The code tells TikZ that I want a line “–” drawn from one (x,y) coordinate to a second coordinate. Multiples of these lines can be drawn in a single line. I have drawn curved lines with a different notation. I tell TikZ to draw from the first (x,y) coordinate “to [out=a,in=b]” where “a” and “b” are angles. This creates a curved line which connects to the previous and next segment at the defined angles. There are many ways to draw curves in TikZ, but for simple figures such as depicted here, this approach is sufficient. Finally, note how each line of the “tikzpicture” code is ended by a semicolon. This line ending is not something that you normally see in LaTeX, so be sure you don’t forget it.

When I compile my code, the slide with the drawing of the MOSFET in TikZ looks like this:

Now let’s add some color to our image. Using TikZ, adding a color is as easy as mentioning a fill color. But this is a special case. When drawing electronic components at the surface level, there are standard colors used for certain things. The standardized colors make it easy for Engineers to understand how a circuit works at a glance. These colors, from the classic VLSI design program “Magic”, are show in the picture (from Prof. Stine’s guide to Magic) below:

I want to use these colors for all of the drawings in my slides and notes. Therefore, I am going to make a new command for the colors in LaTeX. Additionally, since I expect my drawings to overlap at times, I want to give the colors patterns as well. I add the following code to my preamble:

\newcommand{\metalone}{[pattern= horizontal lines, pattern color=blue]}
\newcommand{\metaltwo}{[pattern= vertical lines, pattern color=purple]}
\newcommand{\poly}{[pattern= grid, pattern color=red]}
\newcommand{\pdiff}{[pattern= north east lines, pattern color=orange]}
\newcommand{\ndiff}{[pattern= north west lines, pattern color=green]}
\newcommand{\pwell}{[pattern= crosshatch dots, pattern color=orange]}
\newcommand{\nwell}{[pattern= crosshatch dots, pattern color=green]}
\newcommand{\oxide}{[pattern = bricks, pattern color = olive]}
\newcommand{\silicon}{[fill = white]}
\newcommand{\metalthree}{[fill = teal]}


In this section, I am defining a new custom command for LaTeX with the command name in the first set of curly braces, and the action to be performed in the second set of curly braces. The actions include a pattern and a pattern color in a format acceptable to TikZ notation. All I have to do is include the command in my drawing for the color and pattern to apply. If I decide to change a color later on (maybe metalthree needs to be pink instead of teal), all I have to do is change the command in one location and every instance of the command in the code is changed.

Additionally, since we decided to use patterns with the color fill commands, we need to add a line in the preamble declaring that we are going to use patterns. This is the case for all optional TikZ libraries we use in the future.

When we take a look at the complete code for the MOSFET in TikZ slide, it should look like this:

\documentclass{beamer}

\usepackage{tikz}
\usetikzlibrary{patterns}

\title{\LaTeX~Surface Science and Electronics}
\author{Wesley T. Honeycutt}
\date{\today}

\newcommand{\metalone}{[pattern= horizontal lines, pattern color=blue]}
\newcommand{\metaltwo}{[pattern= vertical lines, pattern color=purple]}
\newcommand{\poly}{[pattern= grid, pattern color=red]}
\newcommand{\pdiff}{[pattern= north east lines, pattern color=orange]}
\newcommand{\ndiff}{[pattern= north west lines, pattern color=green]}
\newcommand{\pwell}{[pattern= crosshatch dots, pattern color=orange]}
\newcommand{\nwell}{[pattern= crosshatch dots, pattern color=green]}
\newcommand{\oxide}{[pattern = bricks, pattern color = olive]}
\newcommand{\silicon}{[fill = white]}
\newcommand{\metalthree}{[fill = teal]}

\begin{document}

\frame{\titlepage}

\frame{\frametitle{MOSFET}
% General n-type mosfet
\begin{tikzpicture}
\draw \pdiff (0,.25) -- (0,3) -- (1,3) -- (1,2.5) to [out=270,in=180] (1.5,2) -- (3.75,2) to [out=0,in=270] (4.25,2.5) -- (4.25,3) -- (6.75,3) -- (6.75,2.5) to [out=270,in=180] (7.25,2) -- (9.5,2) to [out=0,in=270] (10,2.5) -- (10,3) -- (11,3) -- (11,.25) -- (0,.25);
\draw \metalthree (0,0) rectangle (11,.25);
\draw \oxide (4,3) rectangle (7,4);
\draw \metalone (4,4) rectangle (7,4.5);
\draw \ndiff (4.25,3) -- (1,3) -- (1,2.5) to [out=270,in=180] (1.5,2) -- (3.75,2) to [out=0,in=270] (4.25,2.5) -- (4.25,3);
\draw \ndiff (10,3) -- (6.75,3) -- (6.75,2.5) to [out=270,in=180] (7.25,2) -- (9.5,2) to [out=0,in=270] (10,2.5) -- (10,3);
\draw \metalone (1.25,3) rectangle (3,3.5);
\draw \metalone (8,3) rectangle (9.75,3.5);
\end{tikzpicture}
}

\end{document}


Compiling this code will give us this as our second slide: