PCB Prep: cut, drill, and liquid tin

In last week’s post, I discussed a method for DIY PCB etching. This week, I will be continuing in that manner by showing you the final preparation steps I used to get this board ready for soldering including cutting, drilling holes, and protecting the copper with liquid tin.

Cutting and Drilling

Once the boards were completely etched, the holes for through hole parts had to be drilled. These holes were drilled out on a drill press with carbide CNC bits. This part was a challenge, as I did not have a way to punch marks on the copper. Thus, each hole was centered by sight.
Cut and drilled. Good enough for some.
It is much easier to transfer and etch multiple boards onto a single piece of copper-clad FR4 than to do each individually. This is exactly what I did. So once the through-holes were drilled, the individual boards were separated from each other. The FR4 was cut on the shop table saw. As I did not leave much room between the individual boards, I took care to keep the kerf of the blade from touching any copper during the cut.

Protecting the Copper

Copper is a metal which readily undergoes redox reactions in the atmosphere. The copper of a circuit board is no different. If it is left unprotected, the copper will corrode and damage the functionality of the device. Therefore, we must protect it from the atmosphere.

Most PCB fabrication shops apply a mask to the board, covering up all of the leads which do not need to be directly exposed for soldering. The masking materials I have seen are often UV reactive polymers. The etched board is given a thin film of the polymer precursor (often dyed pretty colors, like green), which is then polymerized by exposing the board to intense UV radiation. Unfortunately, we do not currently have any of this material in our shop, so I omitted this step during my fabrication.

Next, in commercially available boards, the contacts are tinned, while the traces are protected by the polymer. Instead of worrying about the pretty polymer covering, the entirety of the copper on my board was tinned as I did not have the luxury of the polymer coat. Tin plating works well to cover the copper, as the tin protects the copper from water vapor while being very solderable (the solders have roughly a ~50% tin content.)While this method is fine for prototyping a DIY board, it is not suitable for end-products. This is chiefly because tin has some odd properties that cause issues with time.

Linguistic and History Aside

The name of the process, tinning, is a throwback to the original method used to protect board contacts, application of a tin solution which coats the copper. These days, there are many possible tinning agents to protect your board from the inexpensive bronze amalgam to the costly solid gold plating.

Back in the good old days (ca. 1650 C.E.) when you wanted tin plate, the tinsmith would dip the entire metal part in molten tin. With the advent of electricity, electroplating was (re-)discovered. This is still a preferred method for many applications. But we want the quick and easy shortcut. So we will use liquid tin.
Liquid tin, nasty stuff.

Chemistry

According to the MSDS, liquid tin is a solution of:

  • Stannous fluoroborate – Sn(BF4)2
  • Fluoroboric acid – HBF4
  • Thiourea – SC(NH2)2

The actual chemical composition is, naturally, not reported by MG Chemicals. There are a few patents available out there for tin immersion solutions such as Liquid Tin, but I make a point of not reading patent literature beyond the title to prevent accidental infringement at a later date. If you wanted to get really DIY, you could probably recreate this solution. Plating solutions follow the same generic formula1. You need a:

  • Metal ion source
  • Reducing agent
  • Complexant
  • Buffer
  • Exaltant
  • Stabilizer

Obviously our metal ion source is Sn(BF4)2 as well as being the buffer source. The acid takes care of the reduction. The thiourea acts as the complexing agent in this case as well as a stabilizer2. All that remains is the exaltant. According to Mellor, an exaltant is a field specific term (I’m guessing based on German) for a reaction accelerator3. While there are several non-toxic organic acids that the makers of liquid tin might use for this purpose, I wonder if the aqueous fluoroborate satisfies this niche.

Back to the Boards

The boards are submerged in the liquid tin solution for a few minutes. As the solution works, rather quickly thanks to our mystery exaltant, you can enjoy the pretty color change from copper to silver. Since the exchange in a liquid tin immersion is surface limited, theoretically you could leave the board in the solution while you work on other things. I was too excited though, so I popped them out right away.
The completed boards.
The boards I made had a white substrate from the copper clad material, so the tin plating doesn’t show up very well in my picture. That’s why I included the picture below of another circuit I tinned that day on flexible Kapton film. The orange really makes that tin pop.
These flex circuits look prettier.

Finished

With the board tinned, it is time to solder on the components. Since I’m a crazy person, I solder the SMD parts on by hand instead of using the oven. The result looks a bit ugly, but it is what’s inside that counts. My completed TB6612FNG board is finally complete.
My hand soldered SMD parts may look ugly, but they work like a dream.

Works Cited

[1] B.D. Barker, Electroless deposition of metals, Surface Technology, Volume 12, Issue 1, 1981, Pages 77-88, ISSN 0376-4583, https://doi.org/10.1016/0376-4583(81)90138-2.

[2] Cassidy, J. E. and Moser, W. and Donaldson, J. D. and Jelen, A. and Nicholson, D. G., Thiourea complexes of tin(II) compounds, Journal of the Chemical Society A: Inorganic, Physical, Theoretical, 1970, Issue 0, pages 173-175, http://dx.doi.org/10.1039/J19700000173. 

[3] Mellor, B.G., Surface Coatings for Protection Against Wear, 2006, Woodhead Publishing Series in Metals and Surface Engineering, ISBN 9781845691561.

DIY PCB Etching

Reasoning

Today, I will be showing you the DIY PCB etching workflow used in the lab where I am working. In the post last week, I discussed the design considerations for a TB6621FNG motor control board. This post will document how the physical PCB was created.

Previously, when I have wanted to produce a PCB, I used a fabrication service. For low-budget projects or personal projects, I used OSH Park. While this service is very cost effective for small prototypes, it takes several weeks for the board to arrive. In projects with a heftier budget where timeliness was an issue, I have used Advanced Circuits’ barebones PCB fabrication service. But what if the project is low-budget and in need of a quick turnaround? Easy: take fate into your own hands with a little DIY PCB etching!

Materials

For this project, you will need:

  • Inkjet Transferring Supplies
    • Inkjet Printer
    • Glossy photo paper
    • Lamination Machine
    • Scissors and tape
  • Etching Solution Bath
    • 1 parts (by volume) Muriatic Acid (12M HCl)
    • 3 part (by volume) 3% Hydrogen peroxide
    • Disposable container made of PE or PP
    • Hot water bath
    • Plastic tongs
  • Acetone
  • Personal protective equipment

Making an Inkjet Transfer

First, you need we prepare our PCB layout for a transfer process. If you are using KiCAD, this is very simple. Go to “plot” your PCB. When the small screen pops up (see image below), the option “mirrored plot” will be grayed out. So first, you must set the plot type to PDF. Then, the “mirrored plot” option will become available.

Note that I have selected to only plot the front layer of copper. Since we can only put a transfer on one side of the board, we can only select one layer at a time. Thankfully, the board I designed is single sided. Note that if you are also etching a back copper layer, you will not need to mirror that plot.

Now, we print four copies of my PCB onto a single sheet of glossy paper. It is important to make more than one copy when you produce a board, as sometimes not everything goes perfectly and you have to throw one of them out.

I wish I had information on the paper I used for this project. Unfortunately, my post-doctoral advisor just found some old stuff that was being removed from the department. The packaging of the ream of paper has no identifying information aside from the 90’s era IBM logo. So, I can’t help you pick the right paper to use. What is important to note about this paper is its glossy photo finish. When the ink is printed onto this kind of paper, the ink remains in a top layer of plastic instead of penetrating fully into the paper. This is thin polymer film is what we will use as the transfer.

Transfer of the transfer

Copper Clad source for DIY PCB etching.

Next, we cut out our prints and tape them upside-down to the copper side of an FR4 board. This material is called “copper clad board”. The material I used in this instance is pictured above. The part number is not available from that supplier at this time, but there are some other versions instead. See here. The type of tape you use does not matter much. I used brown packing tape, but most will be fine. Personally, I would avoid duct tape, because I suspect that would generate gross fumes and make a mess in the next step, but I have no experience to back this suspicion up.

The cheapo laminating machine.

Now, we take the prepared copper clad board and run it through a desktop lamination machine. While other methods for DIY PCB etching might call for a heat gun or hairdryer to affix the transfer to the board, we found that the laminator works best. The board is rotated and passed through the machine multiple times. For our particular materials and equipment, my advisor stated that the transfer must be passed through exactly 7 times, as this is the correct number to affix the transfer to the copper without melting anything.

The printed reverse screen is taped to the copper of the board.

With the transfer on the copper, we give it time to cool down. Once cooled to room-temperature, the board and paper are submerged into warm water. After a moment of soaking, the paper peels off cleanly from the copper clad board, leaving a nice clean transfer.

After washing the transfer paper off.

DIY PCB Etching

Now that our ink has been transferred to the copper clad board, we can begin etching. The etching solution is prepared by a volumetric mixture of 1:3 muriatic acid and hydrogen peroxide in consumer concentrations. Note that these chemicals can be substituted with ~12M HCl and 3% HOOH, should you be in a setting without the consumer versions I mentioned. As always, remember your safety rules. Add acid. This means that you should add acid to the hydrogen peroxide, not the other way around.

One way to accelerate a reaction is to increase the temperature of the solution. Since we are doing this in an inexpensive disposable PE or PP container, directly heating the solution with an electric heater or burner is impractical. Thus, the solution is floated in a hot water bath during the reaction. We used an ice chest which was on hand when we performed this reaction. This high tech etching bath is full of dangerous chemicals, so I recommend putting a lid on the reaction vessel.

High-tech DIY PCB etching bath.

Once you give the solution a few minutes to equalize in temperature with the water bath, you can place the board in the solution. The exposed copper will begin to bubble, and the solution will begin to turn green. After few minutes, the reaction should be complete. Keep an eye on it though. Once the copper is completely etched from the exposed board, remove it from the solution with your plastic tongs and stop the reaction by submerging the board in the water bath. If you leave it too long, the solution will begin to etch the copper you want to keep for the board.

A look inside the high-tech DIY PCB etching bath.

Cleanup

Now that the board is etched and the reaction has been stopped, we can clean up our product. In the image below, we can see that the copper has been completely removed from the exposed areas, but the ink from the transfer remains. This can be cleaned with acetone.

With the copper removed, and the transfer still on.

Use a minimal amount of acetone and a cloth to wipe the board. You may have to do some scrubbing, but the acetone does a good job removing the ink. This process should not be very difficult. Once you are done, you are left with a copper board that is complete.

Acetone washes the transfer ink right off.

Next week, I will be discussing steps I took to make the board from my DIY PCB etching ready for components.

TB6612FNG Motor Control Board

Background

As part of a to-be-announced project I am working on, I ended up designing a new Toshiba TB6621FNG motor control board which is designed to be compatible with the Raspberry Pi. Before I began this design, the lab I am working in had been using controllers based on the Rohm BD6222HFP chip. This is a chip which is well suited to hefty 12V designs. However, we now need something more efficient and less expensive. The TB6612FNG chip is:

    • Less expensive (by ~$1 at single unit scale)
    • Requires more hobbyist friendly supply voltages ( 3-5.5V instead of 6-18V)
    • Provides similar output amperage compared to the Rohm chip.
    • Input current in standby (IIH) averages 35μA less.

    All this lead me to design around the new chip. Of course, breakouts from the usual suspects such as Sparkfun (seen here) and Adafruit (seen here) are available. Adafruit even provides an advanced version which is (in my opinion) over-specialized (see it here). So why did I reinvent the wheel in this case? Because the basic breakout boards are too limited and the advanced version is too limiting.

    Pi Woes

    The GPIO pins on the Raspberry Pi are a wonderful thing. They provide so much room for innovation. However, when you only need one or two specific pins, and those pins are scattered all over the GPIO, it is inconvenient and slightly expensive to design a board with the full 26 pin socket. Instead, selective use of 3-pin servo headers can be used at lower cost. The TB6612FNG motor control board I designed uses this type of design.

    Additionally, there is a problem unique to certain pins of our good ol’ GPIO friend. During boot, pins are not consistently pulled up or down. This can mean that a motor run by these pins may do strange things during boot. If one of those motors is controlling some sort expensive optics as in my case, this is to be avoided. There are a few work around options for this. It is possible to set up a cron job at boot which will set all of the pins to pull up or down, but this may be a challenge to a user with less bash experience. For my project, I need something that allows a user to run the device without worrying about the details. So I implemented a hardware solution. The GPIO pins are pulled down by 100k resistors on my TB6612FNG motor control board.

    An advanced setting was made available to divorce the chip ground from the motor power ground by way of a solder jumper.

    Schematics

    Pictured below is the schematic for my TB6612FNG motor control board. The project was designed with KiCAD.

    TB6612FNG motor control board schematics

    The picture below shows the layout of the board, omitting the back copper plane. I was able to fit all of the traces on one side of the board, so the B.Cu layer is mostly ground plane thermal relief.

    TB6612FNG motor control board copper layout

    Next week, I will show how I made the board.

Dissertation: Development and Applications of Chemical Sensors for the Detection of Atmospheric Carbon Dioxide and Methane

It is a new year, and my dissertation has finally made it past embargoes to publication. Allow me to present: Development and Applications of Chemical Sensors for the Detection of Atmospheric Carbon Dioxide and Methane. You can view the ProQuest entry here. There is a download link to the full text at the bottom of this entry.

Title

Development and Applications of Chemical Sensors for the Detection of Atmospheric Carbon Dioxide and Methane

Abstract

This is a description of the design of a low-power, low-cost networked array of sensors for the remote monitoring of carbon dioxide and methane. The goal was to create a scalable self-powered two-dimensional array for the detection of these gases in a large area. The sensor selection, electronic design, and data communication was studied and optimized to allow for multiple units to form a self-assembling network for acre-scale coverage with minimal human intervention. The final electronic design of the solar-powered units is flexible, providing a foundation for future field deployable remote monitoring devices. Sensors were selected for this application from commercially available models based on low-power, low-cost, market availability, detection range, and accuracy around the global baseline criteria. For environmental monitoring, carbon dioxide sensors are characterized near 400 ppm and methane from 2 to 200 ppm. For both gases, exertions up to several 1000 pm were examined to mimic large releases. An Xbee mesh network of radios was utilized to coordinate the individual units in the array, and the data was transferred in real-time over the cellular network to a dedicated server. The system was tested at a site north of the Oklahoma State campus, an unmanned airfield east of Stillwater, OK, and an injection well near Farnsworth, TX. Data collected from the Stillwater test sites show that the system is reliable for baseline gas levels. The gas injection well site was monitored as a potential source of carbon dioxide and methane leaks due to the carbon dioxide injection process undertaken there for carbon sequestration and enhanced oil recovery efforts. The sensors are shown to be effective at detecting gas concentration at the sites and few possible leak events are detected.

Reference Information

Subject Classification 0485: Chemistry
0486: Analytical chemistry
0494: Physical chemistry
Identifier / keyword Pure sciences
Carbon dioxide
Detection
Enhanced oil recovery
Methane
Remote monitoring
Sensing
Author Honeycutt, Wesley T.
Number of pages 196
Publication year 2017
Degree date 2017
ISBN 9780355396188
Dissertation/thesis number 10276467
ProQuest document ID 1965485293
Advisor Materer, Nicholas F.
Committee members Apblett, Allen W.
Fennell, Christopher J.
Ley, M. Tyler
White, Jeffrey L.
University/institution Oklahoma State University
Department Chemistry
University location United States — Oklahoma
Degree Ph.D.

Download

Here is a download link to the complete dissertation file: Dissertation.pdf

NOTE: This file is a 166.7MB PDF document. Since I am not a rich man, my website is hosted on a slow, inexpensive server. This download may take some time. It may be quicker to download from a library site, but I want to make sure the document is available to everyone.

Greek Philosopher Mask 3

Two weeks ago, I discussed the inspirations for a Greek Philospher mask. Last week, I showed how this mask was built up. This week, my Greek Philosopher mask will be completed with the addition of paint and lacquer.

An Aside About Rocks

The ‘stone’ surface of the Greek Philosopher mask was painted to look similar to marble. To do this, I first set about finding what sort of marble I wished to imitate. In keeping with the faux-historicity of the mask, I decided to base the colors in the marble off of that which was available in the Hellenistic period. Additionally, I wanted to give the stone an aged appearance which fits with the thematic elements discussed in the inspirations post. My Greek Philosopher mask was to be made of material which imitates discolored Parian marble. Marble from the island of Paros is recognizable as a uniform, crystalline white marble (Washington 1898). The picture below depicts a magnified image of Parian marble.

From Washington 1898.  I wonder if that arrow is part of the original?

While no marble ages the same, generally Parian marble ages in such a manner to produce a distinctly orange-hued discoloration. This is possibly due to sub-surface oxalate migration or formation (Pinna 2015). Below are some pictures of discolored Parian marble. The first is a bust of Alexander. The second is Nike of Samothrace.

Bust of Alexander

Nike of Samothrace

The hues present in Parian marble statues is distinct from other sources from the area such as Carrara marble. This is the material used in several recognizable sculptures, such as Michelangelo’s Pietà (pictured below) and the Elgin Marbles. These figures often take on a more gray-hued discoloration with age. This is possibly due to fungal and/or bacterial growth on the surface (Marvasi 2008, Konkol 2009).

Michelangelo's Pietà

Stone in Paint

To produce the marble effect I wanted, I used a variant of a technique called Scagliola. To employ this traditional method for my modern Greek Philosopher mask, I mixed white latex paint with plaster of paris and acrylic paints which acted as pigments. While the surface was wet with the paint, I drew in paints of another pigment to form lines. Then, the light tone of the first few coats was given a dabbed on patina with warm-toned grays and browns to mimic approach the aged Parian marble look I wanted. Finally, carbon soot was rubbed on the dried paint.

After the painting was complete, I added highlighting by marring the surface. A nail was used to scratch the painted surface down to the bottom layers of the scagliola (beneath the dabbed gray, brown, and carbon). These scratches were added in the recessed corners of the surface such as the beard and hair. Additional scratches were added in a haphazard fashion to the smoother surfaces. By using the scratches on the surface, a more aged look is achieved. Applying the scratches to recesses of the surface of the mask mimics the patterns of marble which has been discolored due oils from the skin rubbing on the surface.

Greek Philosopher mask with painted and scratched surface

Sealed and Shined

As the Greek Philosopher mask was intended to be functional, the completed surface needed a sealant to prevent the paint from being removed or damaged during wear. Several coats of a water-tight lacquer was applied to the mask. This would prevent spills or rain from damaging the surface, and it would prevent sweat from damaging the interior. The lacquer I used gave the mask the appearance of a polished sheen. If I was to attempt this again, I am not certain I would use a glossy lacquer, as a matte coat might have been more appropriate for a stony surface.

A shiny lacquer coating

The Greek Philosopher Mask used to play Hades

The complete mask was officially shown to the public at Halloween party. Accommodating the wish of my date for a couple’s costume, I dressed as Hades and she as Persephone. The entire costume was a hit, the mask especially. I admit, I still wear the mask from time to time. Since this is one of my favorite works, I find it hard to resist popping it on for a good session of pondering.

Hades and Persephone pose at a party.  Remember to never drive drunk, always have Charon give you a ride back across the river.

Works Cited

Washington, Henry S. “The Identification of the Marbles Used in Greek Sculpture.” American Journal of Archaeology, vol. 2, no. 1/2, 1898, pp. 1–18. JSTOR, JSTOR, www.jstor.org/stable/496773.

Pinna, D., Galeotti, M. & Rizzo, A. herit sci (2015) 3: 7. https://doi.org/10.1186/s40494-015-0038-1

M. Marvasi, F. Donnarumma, A. Frandi, G. Mastromei, K. Sterflinger, P. Tiano, B. Perito, Black microcolonial fungi as deteriogens of two famous marble statues in Florence, Italy, In International Biodeterioration & Biodegradation, Volume 68, 2012, Pages 36-44, ISSN 0964-8305, https://doi.org/10.1016/j.ibiod.2011.10.011.

Nick Konkol, Chris McNamara, Joe Sembrat, Mark Rabinowitz, Ralph Mitchell, Enzymatic decolorization of bacterial pigments from culturally significant marble, In Journal of Cultural Heritage, Volume 10, Issue 3, 2009, Pages 362-366, ISSN 1296-2074, https://doi.org/10.1016/j.culher.2008.10.006.

SiC Logic: A Rejected Proposal

This is a proposal I wrote and submitted to the July 2017 cycle of the NASA NPP program to work on development of SiC logic for a Venusian satellite project.. It was rejected and I went another direction. The SiC logic proposal idea was generally well received. While many of the reviewers comments could have been addressed in a treatise with ample page limits, there was little I could do about the primary concern. It is clear that the reviewers would have been more comfortable awarding the postdoctoral position to someone who had worked with silicon carbide before, rather than explaining in theory and going for on-the-job experience. This is a fair assessment that I suspect I will never be able to address, as SiC logic is not a common enough field to get easy exposure too.

So with the understanding that I will likely not be able to work on this in the future, I would like someone else to pick up the reins and move forward with the project. This is a very important project that has many applications, as will be addressed below. I urge readers to STEAL THIS WORK. Therefore, I am taking the time to release this rejected proposal on my site to allow others to learn from it and, hopefully, continue the proposed project. The full text of the project is below, modified from the original to fit the current medium.

As always, feel free to contact me for info or to chat about this.  My contact info can be found on the CV page.


Development of Logical Circuitry using Silicon Carbide Substrates for Control Circuits in Harsh Environments

by

Wesley T. Honeycutt

Title of Research Opportunity: SiC Circuit and Device Design and Fabrication

NASA Center: Glenn Research Center

1. Statement of problem

Recently, NASA has begun prioritizing an exploratory mission to Venus [1], including a surface lander [2]. Previous landers from the Venera program by the USSR were only able to last, at most, two hours on the unforgiving Venusian surface [3]. The extreme temperatures and oxidative atmosphere of the planet’s surface mean it is very difficult for current electronic systems to perform for extended periods. While a wealth of new high temperature and pressure sensing instruments have been developed as part of the Venus Exploration Analysis Group (VEXAG), the glue electronics to control and operate such a lander are still elusive [4].
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The development of silicon carbide (SiC) semiconductor devices has gained increasing popularity in the past 20 years, yet the technology lacks the wide breadth of available devices which competing substrates currently offer. Far from the first light emitting diode [5] [6] which was originally made in SiC, today SiC can be found in many high power applications. Recent developments have even allowed the creation of power switching devices with high-voltage junction temperature tolerance up to 1200 V in both JFET and MOSFET designs [7] [8]. Current SiC logical devices are produced using JFET technology. Core logic gates such as the inverter, NAND, and NOR have been demonstrated in both depletion mode [9] and enhancement mode [10] SiC JFET. Despite recent demonstrations of a ring oscillator and development of 100’s scale transistor level logic using SiC JFET technology [11], there is a dearth of advanced logic designs for SiC circuits which would further the NASA Venus lander objectives. The goal of this proposed work is to develop discrete digital logic devices using SiC substrates and patterning.

2. Background and relevance to previous work

Silicon carbide has several interesting properties that make it an attractive semiconductor platform for devices intended to withstand harsh environments. At standard atmospheric pressures, SiC remains crystalline with no defects at temperatures up to 2760 °C before partial sublimation [12]. At higher pressures, this temperature stability increases. Under 100 atm, similar to the pressure at the surface of Venus, SiC remains solid up to 2830 °C before melting. Individual junctions of p-doped and n-doped SiC material have a much higher tolerance for heat than more commonly used substrates such as Si. This is because the optimum working temperature of SiC is very close to the highest normal mode vibrational temperature, or band gap [13]. Microelectromechanical systems (MEMS) based on SiC have been established as a viable device for some time [14], and some developed MEMS devices are pushing temperature limits in sensors [15]. Logic gates manufactured from SiC can take advantage of this property by creating devices which tolerate high voltage switching, a task which produces a large amount of heat [16]. The converse can be true as well: it is possible to make low power logic gates that tolerate extreme temperatures.

Additionally, SiC has been shown to be particularly resilient against radiation damage. Circuits made of SiC have been reported to exhibit much lower rates of carrier damage due to deep material defects caused by neutron flux, with McGarrity et al. reporting 1/3 of the damage compared to Si based devices at doses of 1016 neutrons/cm2 [17]. This makes SiC technology attractive for radiation heavy environments, including satellites and exploratory vehicles. The large gate sizes in current SiC technology compared to modern CMOS feature sizes makes the SiC further resistant to radiation effects [18]. If this material is used for the sensitive electronic equipment, it is possible to have reduced failure rates with current design specifications. Furthermore, it is possible that future devices using this technology may require less device redundancy for radiation hardening purposes, making it possible to create exploratory vehicles with greater computational power and reduced power consumption.

Logical units for SiC are designed by the NASA Silicon Carbide Electronics and Sensors group using depletion mode JFET technology on both 4H-SiC and 6H-SiC wafers. At the simplest level of description, an n-type JFET, the most durable and stable type for high temperature operation [11], is a transistor gate with the drain and source connected to an n-type substrate with a p-type gate separated by a depletion layer. A detailed diagram of the current archetypal SiC JFET layers can be found in the literature [19]. These JFETs are normally ON devices which switch OFF when a voltage applied to the gate passes a certain threshold in a reverse biased regime. Due to this design, the source requires a negative voltage, making the HIGH and LOW bits ground and a negative voltage, respectively. As certain parts of a logical array require a positive voltage, a JFET logic circuit is necessarily more complex to design due to the presence of an additional power rail. Further complications arise from the body bias effect based on the substrate voltage [20] and radially dependent resistivity observed in printed wafers [19].

As a physical chemist, I have an outside perspective on device function at the gate interface level which allows for a critical approach to the challenges posed by innovative logic design. My previous experience with silicon based control systems has demonstrated that I am capable at computer aided design (CAD) of electronic systems [21]. In addition to my design experience, I have also used modeling programs such as SPICE to characterize the behavior of a Fourier transform device for monitoring sample conductivity. Modern developments in microcontroller prototyping boards allow for integration of one device to test another. My previous work gave me experience with prototype evaluation of electronic systems and bringing a scientific approach to an engineering problem. Particularly, previous designs for sensors deployed in unpredictable climates have made me conscious of the need for devices built to tolerate these conditions including temperature dependent conductivity sensors [22]. As a scientist who enjoys developing devices for monitoring and evaluating physical and chemical properties, the challenges posed by SiC JFET design appeal to my desire to broaden my skills.

3. General methodology, procedures to be followed, and timeline for completion of each step

The goal of this proposed work is to develop logic circuits required for a low power monitoring device tolerant to harsh conditions by application of known computing architecture to the emerging silicon carbide technology. At the highest level of abstraction, a device of this nature requires a central processing unit (CPU), level shifters, analog to digital converters (ADC), switched power supply units (PSU), and memory. Certain portions of this list, including level shifters [9], ADC [23], and PSU [24], have been demonstrated in previous research. In the case of a modern application, a single package microprocessor can handle most of these tasks. However, minimal work has been done creating complex logic for the CPU in SiC. The development of this device must start from a basic level, designing the subcomponents of the CPU individually.

A CPU can be generalized as a combination of individual logic units, primarily these are registers and arithmetic logic units (ALU). The goal of this proposal is to develop the technology in SiC JFET for both of these logic units to create a functional 8-bit microprocessor.

3.1 Register

Figure 1

Decreasing level of register architecture in SiC logic

This is an example register design showing the design hierarchy. Part 𝒶 shows the primary user accessible 8-bit registers included in the design of the popular Intel 8085 chip [25]. Part 𝒷 shows detail of one register from part 𝒶 [26] [27]. Each bit of the register is a flip-flop which adjusts the value from D to Q for each bit on in a clock cycle. Part 𝒸 shows one of these flip-flops. A flip-flop is composed of two latches, a master and a slave, which copy D to Q on the rising edge of the clock cycle. This saves the state of the flip-flop at all other times. Part 𝒹 shows one of the latches, a simple logic circuit consisting of one NOT, two ANDs, and two NORs in a bistable arrangement. Part ℯ shows a diagram of one CMOS NOR gate depicted in part 𝒹 as they would be designed for patterning on the SiC surface using the program MAGIC [28]. In short: multiple of ℯ make up 𝒹, which make up 𝒸, which make up 𝒷, which make up 𝒶.

The register is a logic unit which is included in many important CPU and device components such as the primary register, memory, instruction set, and program counter. To construct this unit, we must reduce this piece down to its relatively simpler components. The register is a series of clock synchronized flip-flops, a flip-flop is a pair of latches, a latch is simply a pair of NOR gates connected in a certain manner, and a NOR gate is constructed from a few individual transistors. Figure 1 shows the decreasing levels of abstraction from the register of a popular integrated circuit to the layers and doping of a single NOR gate designed for CMOS technology. The transistor technology for JFET SiC gates have been previously demonstrated for NOR gates, making the technology scale up possible.

Due to the synchronous nature of the register and the importance of timing in computing, each device will be rigorously analyzed as it is created and tested. As it is impractical to directly measure single gate delay, a value which is often on the scale of picoseconds, it is useful to estimate the rise and fall of a signal through a gate using computational models and values of capacitance and current for each interconnect [29]. The delay for multiple equivalent gates is additive at scale, making the averaged delay over multiple gates in a device a calculable quantity with simple instrumentation. The averaged gate speed can be measured by construction of an array of latches acting asynchronously. This will be used to verify computationally calculated values.

Keeping with the “bottom-up” approach to design on the SiC substrate, the first task will be designing and verifying a single bit flip-flop, which has not been reported in literature. The patterned device will be characterized by tests to determine the ability to retain and replace the bit over multiple clock cycles. As SiC devices are being sought to operate in harsh conditions, tests will be undertaken to determine the bit retention ability of the flip-flop at a range of temperatures from standard conditions to >500 °C. Testing of the device can take place with a voltage monitor (capable of determining bit state) at short time scales and a local RC oscillator (as oscillators must be close to the circuit to prevent return current, making an external crystal oscillator impractical for high temperature tests). The second task will be to scale this device up to a full 8-bit register. Findings from the first task will be used to determine the design of this circuit, and it will be tested and verified in a similar manner.

3.2 Arithmetic Logic Unit

Another essential component of the CPU is the Arithmetic Logic Unit (ALU). This is an umbrella term for portion of the processor which performs simple arithmetic operations such as addition, subtraction, multiplication, division, and comparison. Each of these operations requires a distinct circuit. The addition and subtraction circuitry will be designed in the form of a carry-lookahead adder (chosen for the ability to perform faster calculations than many other adder circuits, a property which will be valuable in lifetime-limited missions), using two’s compliment values for subtraction operations. The multiplication and division operations will be performed on circuitry designed using logical and arithmetic shifters. Equality comparators are simple ANDs of a number of XNOR gates, which can be constructed from the NAND and NOR gates available in SiC JFET. Magnitude comparators are a variant of subtractors. All of these have well documented logical designs which can be applied to SiC systems.

Simple arithmetic circuits are used throughout the computer system. For example, operations are performed based on orders delivered by Operation Codes (Opcodes) from the program register. These instructions must be interpreted by the logic of the device by arithmetic means. For example, an adder is used to determine the address of the next instruction from the program counter, and a control ALU is utilized to compute the memory address of data to be operated upon by the CPU. With a working register established, it will be necessary to develop a way to utilize the register directly by furnishing it with operations. The development goal of designing a working ALU furthers the overarching goal of creating a working processor, as the individual components of the ALU are used in many places.

The first task of the ALU portion of this proposal is to demonstrate a simple half-adder circuit patterned in SiC. The half-adder will be fed alternating values of HIGH and LOW on both inputs to determine if a correct value is generated for the output and/or the carry of the circuit. The input for this circuit will be generated by an external microcontroller such as an Arduino prototyping board timed to send the signal pulses at regular intervals and check the answers. The Arduino will log the inputs, output, and carry from this circuit to check for errors. This experiment will be repeated in both standard conditions and harsh conditions in excess of 500 °C to simulate real operation. The Si based Arduino signal generation and logging can be isolated from the elevated temperature conditions since HIGH and LOW signals are not subject to the same trace length constraints as oscillators. Success of the circuit will be determined by continuous operation without errors with a lifetime to match previously explored logical units [30], discussed further in Section 5. The next task will be to scale up to an 8-bit full adder, then to a carry-lookahead adder which will be tested in the same manner.

Comparators and shifters will be tested in a similar “bottom-up” manner and constraints as the adder. For the comparator, initial tests will be performed on a simple 2-bit comparator, then scaled up to a full 8-bit comparator. The first bit shifter will be a simple array shifter of 2-bits, tested by cycling the bit shift by one unit over time. The scaled up version of the shifter will be tasked with performing full 8-bit shift operations. Tests will be performed at a range of temperature conditions and deemed successful for continuous operation without errors, similar to the other proposed units of the ALU.

4. Explanation of new or unusual techniques

The proposed work is unique in that it uses SiC for logical device fabrication. There are very few devices which use this technology, and use of substrate materials outside of Si in CMOS design is uncommon due to industry focus on small feature sizes and high computational power. While this is a new and exciting area of research, there will be few novel techniques implemented at this stage. The design flow for computers at the Si level is so well documented that many university level research institutions offer courses on the most up-to-date processes available. However, the technology for SiC devices is young compared to Si devices, many of these modern methods make use of architecture and design technology not prepared for the simplicity of SiC. Therefore, a “back-to-basics” approach is more suitable for this project. The “back-to-basics” approach will favor the use of the original VLSI work pioneered by Mead and Conway, and their contemporaries [31] [32] [33].

While much of the design for modern integrated circuits is handled by computational algorithms, few such mathematical models are available for the SiC substrate. The current state of circuit simulation makes use of NMOS SPICE models with certain parameters ignored [11]. Instead, a more traditional approach to device design must be considered. Masks for experimental devices will require manual generation based on traditional standard for VLSI device production pioneered by Mead and Conway [31]. Previous work by the SiC group at NASA has produced some important values for device modeling including size constraints. Physical constants observed in this work will be used to further develop a custom technology profile for SiC in a VLSI design program such as MAGIC [28]. By recording these parameters, it is possible to approach the algorithmic simplicity enjoyed by traditional substrate devices, establishing Electronic Design Automation (EDA). The modularity and regularity inherent to the nature of computer design makes these values extremely valuable as the overarching project scales up. Furthermore, VLSI EDA programs can be used in conjunction with SPICE to simulate the designed circuits at the pattern level [34].

5. Expected results and their significance and application

The qualifications for an individual circuit success were previously mentioned in Section 3. Generally, these success criteria can be divided into data retention time for register devices and continuous error-free operation time for ALU related devices. Some electronic properties are temperature dependent, such as resistance [19] and band-gap [35]. Therefore, it is critical to test circuits designed for optimal operation at one temperature over the range of possible operations temperatures. These tests are to be replicated at both standard temperatures and temperatures found in harsh conditions, such as the surface of Venus, using lab ovens.

A successful register is a device which can retain the stored data over many clock cycles, and change each bit in a timely manner on the rising edge of a single clock cycle. To determine the size of this clock cycle, we look to a reference point, such as a previous lander. The Sojourner Rover utilized a variant of the Intel 8085 chip, the 80C85, running at a clock speed of 2 MHz} [36]. The manufacturer reported maximum clock speed of this CPU is 5 MHz} [37]. Therefore, for the purposes of this test, the success factor will assuming an acceptable operation speed of 2 MHz} with an optimum operation speed of 5 MHz}. If we assume that the bit stored in the flip-flop is either modified on each clock cycle or stored for the clock cycle, and we assume that the chance for a bit to be either 0 or 1 is equal, then we can be 99% confident the longest a bit will be stored in a single flip-flop is 7 clock cycles. Therefore, the produced register will be adequately successful if it can retain a bit for 350 ns and exceed success if it can retain a bit for 1.4 μs.

A successful ALU is a device which can perform the requested operation quickly, with no errors. In a surface level lab with minimal radioactive sources, it should be expected that an adder or bit shifter would work consistently. However, no device is perfect, and chip manufacturers are hesitant to publish failure rates in their devices. Certain failure modes, such as electromigration, are tested for using temperature acceleration. However, the original draw of SiC circuits is the high temperature stability, reducing the likelihood of this failure path [38]. With the lack of benchmarks for ALU failure and the high temperature stability expectation which can accelerate further testing, the success metric will be based on the previous performance reported by the Hunter group, including a thousand hour lifetime of an oscillator at 500 °C [30]. The ALU produced in the course of the work in this proposal will be considered a success if the error-free lifetime exceeds 1000 h, the time reported by Spry et al.

In the event the devices fail to pass benchmarks for the register, ALU, or their preceding variants, efforts will be made to determine the cause of the issue. Previous circuit issues which have been a cause of concern in the past, such as the micropipe defects in SiC devices [38], have been analyzed in detail [39] based on “failed” experiments. This provides much needed data for future improvements on the material. Circuits which do not meet benchmark expectations will be analyzed by electron microscopic techniques for sources of damage, much like the previously mentioned failure was determined to be due to oxide cracking in the thousand hour test [30]. These sources of failure can provide more evidence to shed light on the cause of such defects in SiC systems.

The technology developed for this work has far-reaching applications. There have been few complicated logic devices made in SiC [30]. A successful register and ALU would open the doors to further development in this material, eventually leading to the eventual development of a single-cycle microprocessor CPU with high temperature and radiation resistance. Processors in this material would be very attractive for future space-faring missions and use in extreme terrestrial environments. The individual building blocks produced by this work can also be used as a basis for other SiC devices. For example, the development of a successful 8-bit register would naturally lead to the development of ROM and RAM with similar configurations. The modularity and repeatability of these devices makes it relatively simple to drop a successful gate design from one project to the next. By designing these devices in a prevalent, open-source VLSI EDA environment, the parameters explored in these designs would be available to future designers working with this technology.

6. References/Citations

[1] R Herrick, K Baines, M Bullock, G Chin, B Grimm, W Kiefer, S Mackwell, K McGouldrick, B Sharpton, S Smerkar, and others. Goals Objectives and Investigations for Venus Exploration. Venus Exploration Analysis Group (VEXAG), 2014.

[2] T Kremic, GW Hunter, PG Neudeck, DJ Spry, GE Ponchak, GM Beheim, RS Okijie, MC Scardelletti, JD Wrbanek, DM Vento, and others. Long-Life In-Situ Solar System Explorer (LLISSE) Probe Concept and Enabling High Temperature Electronics. In Lunar and Planetary Science Conference, volume 48, 2017.

[3] Donald M Hunten. Venus. University of Arizona Press, 1983.

[4] Jeff Balcerski. Venus Science Priorities for Laboratory Measurements and Instrument Definition Workshop Report. Technical report, National Institute of Aerospace, Langley, VA, April 2015.

[5] H. J. Round. A Note on Carborundum. Electrical World, 49(6):309, February 1907.

[6] O. V. Losev. Luminous carborundum detector and detection with crystals. Telegrafiya i Telefoniya bez Provodov, 44, 1927.

[7] R. Siemieniec and U. Kirchner. The 1200V direct-driven SiC JFET power switch. In Proceedings of the 2011 14th European Conference on Power Electronics and Applications, pages 1–10, August 2011.

[8] K. Mino, S. Herold, and J. W. Kolar. A gate drive circuit for silicon carbide JFET. In Industrial Electronics Society, 2003. IECON ’03. The 29th Annual Conference of the IEEE, volume 2, pages 1162–1166 Vol.2, November 2003.

[9] M.J. Krasowski. N Channel JFET Based Digital Logic Gate Structure. Google Patents, March 2010.

[10] H. Habib, N.G. Wright, and A.B. Horsfall. Complementary JFET Logic for Low-Power Applications in Extreme Environments. In Silicon Carbide and Related Materials 2012, volume 740 of Materials Science Forum, pages 1052–1055. Trans Tech Publications, March 2013.

[11] Phillip G. Neudeck, David J. Spry, and Liangyu Chen. First-Order SPICE Modeling of Extreme-Temperature 4H-SiC JFET Integrated Circuits, May 2016.

[12] Vera Haase, Gerhard Kirschstein, Hildegard List, Sigrid Ruprecht, Raymond Sangster, Friedrich Schröder, Wolfgang Töpper, Hans Vanecek, Werner Heit, Jürgen Schlichting, and Hartmut Katscher. The Si-C Phase Diagram. In Vera Haase, Gerhard Kirschstein, Hildegard List, Sigrid Ruprecht, Raymond Sangster, Friedrich Schröder, Wolfgang Töpper, Hans Vanecek, Werner Heit, Jürgen Schlichting, Hartmut Katscher, Raymond Sangster,
and Friedrich Schröder, editors, Si Silicon: System Si-C. SiC: Natural Occurrence. Preparation and Manufacturing Chemistry. Special Forms. Manufacture. Electrochemical Properties. Chemical Reactions. Applications. Ternary and Higher Systems with Si and C, pages 1–5. Springer Berlin Heidelberg, Berlin, Heidelberg, 1985.

[13] V.E. Chelnokov and A.L. Syrkin. High temperature electronics using SiC: Actual situation and unsolved problems. E-MRS 1996 Spring Meeting, Symposium A: High Temperature Electronics: Materials, Devices and Applications, 46(1):248–253, April 1997.

[14] Pasqualina M Sarro. Silicon carbide as a new MEMS technology. Sensors and Actuators A: Physical, 82(1–3):210–218, May 2000.

[15] R. S. Okojie, C. Blaha, D. Lukco, V. Nguyen, and E. Savrun. Zero offset drift suppression in SiC pressure sensors at 600 x00B0;C. In 2010 IEEE Sensors, pages 2269–2274, November 2010.

[16] C. E. Weitzel, J. W. Palmour, C. H. Carter, K. Moore, K. K. Nordquist, S. Allen, C. Thero, and M. Bhatnagar. Silicon carbide high-power devices. IEEE Transactions on Electron Devices, 43(10):1732–1741, October 1996.

[17] J. M. McGarrity, F. B. McLean, W. M. DeLancey, J. Palmour, C. Carter, J. Edmond, and R. E. Oakley. Silicon carbide JFET radiation response. IEEE Transactions on Nuclear Science, 39(6):1974–1981, December 1992.

[18] Quming Zhou and Kartic Mohanram. Transistor sizing for radiation hardening. In Reliability Physics Symposium Proceedings, 2004. 42nd Annual. 2004 IEEE International, pages 310–315. IEEE, 2004.

[19] Philip G Neudeck, David J Spry, and Liang-Yu Chen. First-order SPICE modeling of extreme -temperature 4H-SiC JFET integrated circuits. Additional Papers and Presentations, 2016(HiTEC):000263–000271, 2016.

[20] Philip G Neudeck, David J Spry, and Liangyu Chen. Experimental and theoretical study of 4H-SiC JFET threshold voltage body bias effect from 25◦ C to 500◦ C. 2015.

[21] Wesley T. Honeycutt. Development and Applications of Chemical Sensors for the Detection of Atmospheric Carbon Dioxide and Methane. Dissertation, Oklahoma State University, Stillwater, Oklahoma, May 2017.

[22] Wesley T. Honeycutt, M. Tyler Ley, and Nicholas F. Materer. A Comparison of the Properties of Selected Commercially Available, Low-cost Carbon Dioxide and Methane Gas Concentration Sensors. Sensors Journal IEEE, 2017 [Submitted].

[23] Raheleh Hedayati, Luigia Lanni, Bengt Gunnar Malm, Ana Rusu, and Carl-Mikael Zetterling. A 500◦ C 8-b Digital-to-Analog Converter in Silicon Carbide Bipolar Technology. IEEE Transactions on Electron Devices, 63(9):3445–3450, 2016.

[24] Saleh Kargarrazi, Luigia Lanni, Stefano Saggini, Ana Rusu, and Carl-Mikael Zetterling. 500◦ C bipolar SiC linear voltage regulator. IEEE Transactions on Electron Devices, 62(6):1953–1957, 2015.

[25] Intel Corporation. 8080/8085 Assembly Language Programming Manual. Intel Corporation, Santa Clara, 1978.

[26] David Harris and Sarah Harris. Digital Design and Computer Architecture. Elsevier, 2012.

[27] David A. Patterson and John L. Hennessy. Computer Organization and Design: The Hardware/Software Interface. Newnes, 2013.

[28] John K Ousterhout, Gordon T Hamachi, Robert N Mayo, Walter S Scott, and George S Taylor. The magic VLSI layout system. IEEE Design ∧ Test of Computers, 2(1):19–30, 1985.

[29] Brajesh Kumar Kaushik, Sankar Sarkar, and R.P. Agarwal. Waveform analysis and delay prediction for a CMOS gate driving RLC interconnect load. System-Level Interconnect Prediction, 40(4):394–405, July 2007.

[30] David J Spry, Philip G Neudeck, Liang-Yu Chen, Dorothy Lukco, Carl W Chang, Glenn M Beheim, Michael J Krasowski, and Norman F Prokop. Processing and characterization of thousand-hour 500◦ C durable 4H-SiC JFET integrated circuits. Additional Papers and Presentations, 2016(HiTEC):000249–000256, 2016.

[31] Carver Mead and Lynn Conway. Introduction to VLSI Systems, volume 1080. Addison-Wesley Reading, MA, 1980.

[32] Douglas A. Pucknell and Kamran Eshraghian. Basic VLSI Design: Systems and Circuits. Prentice-Hall, Inc., 1988.

[33] Michael Slater. Microprocessor-Based Design: A Comprehensive Guide to Effective Hardware Design. Prentice-Hall, Inc., 1987.

[34] Laurence W. Nagel and D.O. Pederson. SPICE (Simulation Program with Integrated Circuit Emphasis). Technical report, EECS Department, University of California, Berkeley, April 1973.

[35] Y. P. Varshni. Temperature dependence of the energy gap in semiconductors. Physica, 34(1):149 – 154, 1967.

[36] null. Mars Pathfinder FAQs – Sojourner. https://mars.nasa.gov/MPF/rover/faqs_sojourner.html#cpu, April 1997.

[37] OKI Semiconductor. MSM80C85AHRS/GS/JS, January 1998.

[38] J. B. Casady and R. W. Johnson. Status of silicon carbide (SiC) as a wide-bandgap semiconductor for high-temperature applications: A review. Solid-State Electronics, 39(10):1409 – 1422, 1996.

[39] P. G. Neudeck and J. A. Powell. Performance limiting micropipe defects in silicon carbide wafers. IEEE Electron Device Letters, 15(2):63–65, February 1994.

Giant Robber Fly Eating a Cicada

I took a lovely picture this summer of a giant robber fly eating a cicada. The picture was taken in Washington county, Oklahoma. I observed the take-down myself while working in the garage. The robber fly ambushed the cicada while it was sitting on an overhanging branch of the nearby hackberry tree.

Giant robber fly eating a cicada

In the above picture, the cicada is still alive. The panicked trills and beating of the wings allowed for me to easily find where the pair landed. The giant robber fly eating a cicada in this picture is of the genus Promachus. The species is difficult to know for certain without detailed observation of the specimen, but it appears to bear similar traits to Promachus hinei based on information available from BugGuide. Promachus hinei’s range extends through Oklahoma, making this a reasonable candidate. The yellow and black pattern, detailed in this picture, appears to be a distinctive trait.

LaTeX: Drawing MOSFET in TikZ – Labels and Animation

Continuing from last week’s post, this week we will be adding labels to our MOSFET in TikZ and adding slide animations with Beamer.

As a reminder, last week we drew our image of a MOSFET in Tikz before adding colors. The colors we added were based on the materials used in each part of the n-type MOSFET. Now let’s add some labels to make sure that anyone we present this image to can understand what is going in.

Centered Labels

Now we take the code from last week and add “nodes” to certain of our shapes. We tell these nodes to have certain text and compile.

\documentclass{beamer}

\usepackage{tikz}
	\usetikzlibrary{patterns}

\title{\LaTeX~Surface Science and Electronics}
\author{Wesley T. Honeycutt}
\date{\today}

\newcommand{\metalone}{[pattern= horizontal lines, pattern color=blue]}
\newcommand{\metaltwo}{[pattern= vertical lines, pattern color=purple]}
\newcommand{\poly}{[pattern= grid, pattern color=red]}
\newcommand{\pdiff}{[pattern= north east lines, pattern color=orange]}
\newcommand{\ndiff}{[pattern= north west lines, pattern color=green]}
\newcommand{\pwell}{[pattern= crosshatch dots, pattern color=orange]}
\newcommand{\nwell}{[pattern= crosshatch dots, pattern color=green]}
\newcommand{\oxide}{[pattern = bricks, pattern color = olive]}
\newcommand{\silicon}{[fill = white]}
\newcommand{\metalthree}{[fill = teal]}

\begin{document}

	\frame{\titlepage}
	
	\frame{\frametitle{MOSFET}
		% General n-type mosfet
		\begin{tikzpicture}
		\draw \pdiff (0,.25) -- (0,3) -- (1,3) -- (1,2.5) to [out=270,in=180] (1.5,2) -- (3.75,2) to [out=0,in=270] (4.25,2.5) -- (4.25,3) -- (6.75,3) -- (6.75,2.5) to [out=270,in=180] (7.25,2) -- (9.5,2) to [out=0,in=270] (10,2.5) -- (10,3) -- (11,3) -- (11,.25) -- (0,.25) node {p-type};
		\draw \metalthree (0,0) rectangle (11,.25) node {Si Substrate};
		\draw \oxide (4,3) rectangle (7,4) node {oxide};
		\draw \metalone (4,4) rectangle (7,4.5);
		\draw \ndiff (4.25,3) -- (1,3) -- (1,2.5) to [out=270,in=180] (1.5,2) -- (3.75,2) to [out=0,in=270] (4.25,2.5) -- (4.25,3) node {n-type};
		\draw \ndiff (10,3) -- (6.75,3) -- (6.75,2.5) to [out=270,in=180] (7.25,2) -- (9.5,2) to [out=0,in=270] (10,2.5) -- (10,3) node {n-type};
		\draw \metalone (1.25,3) rectangle (3,3.5);
		\draw \metalone (8,3) rectangle (9.75,3.5);
		\end{tikzpicture}
	}

\end{document}

This gives us the following image with ill-placed text:

Ill-placed text on our MOSFET

The text looks odd because the node location in TikZ defaults to the last point in the drawing. We can tell it to place the node in a certain location with respect to this anchor point. Additionally, I might want to change some other properties such as text color for my labels. This can all be done in brackets after declaring the node. Now my code becomes:

\documentclass{beamer}

\usepackage{tikz}
	\usetikzlibrary{patterns}

\title{\LaTeX~Surface Science and Electronics}
\author{Wesley T. Honeycutt}
\date{\today}

\newcommand{\metalone}{[pattern= horizontal lines, pattern color=blue]}
\newcommand{\metaltwo}{[pattern= vertical lines, pattern color=purple]}
\newcommand{\poly}{[pattern= grid, pattern color=red]}
\newcommand{\pdiff}{[pattern= north east lines, pattern color=orange]}
\newcommand{\ndiff}{[pattern= north west lines, pattern color=green]}
\newcommand{\pwell}{[pattern= crosshatch dots, pattern color=orange]}
\newcommand{\nwell}{[pattern= crosshatch dots, pattern color=green]}
\newcommand{\oxide}{[pattern = bricks, pattern color = olive]}
\newcommand{\silicon}{[fill = white]}
\newcommand{\metalthree}{[fill = teal]}

\begin{document}

	\frame{\titlepage}
	
	\frame{\frametitle{MOSFET}
		% General n-type mosfet
		\begin{tikzpicture}
		\draw \pdiff (0,.25) -- (0,3) -- (1,3) -- (1,2.5) to [out=270,in=180] (1.5,2) -- (3.75,2) to [out=0,in=270] (4.25,2.5) -- (4.25,3) -- (6.75,3) -- (6.75,2.5) to [out=270,in=180] (7.25,2) -- (9.5,2) to [out=0,in=270] (10,2.5) -- (10,3) -- (11,3) -- (11,.25) -- (0,.25) node [midway,above] {p doped Si};
		\draw \metalthree (0,0) rectangle (11,.25) node [midway, color=white]
		 {Si Substrate};
		\draw \oxide (4,3) rectangle (7,4) node [pos=.5,font=\bf\Large] {oxide};
		\draw \metalone (4,4) rectangle (7,4.5);
		\draw \ndiff (4.25,3) -- (1,3) -- (1,2.5) to [out=270,in=180] (1.5,2) -- (3.75,2) to [out=0,in=270] (4.25,2.5) -- (4.25,3) node at (2.625,2.5) [align=center] {n-type};
		\draw \ndiff (10,3) -- (6.75,3) -- (6.75,2.5) to [out=270,in=180] (7.25,2) -- (9.5,2) to [out=0,in=270] (10,2.5) -- (10,3) node at (8.375,2.5) [align=center] {n-type};
		\draw \metalone (1.25,3) rectangle (3,3.5);
		\draw \metalone (8,3) rectangle (9.75,3.5);
		\end{tikzpicture}
	}
	
\end{document}

In this case, I have added some alignment options for different locations.

  • For the silicon substrate, I have told the node [midway, color=white] so the text appears in the middle of the rectangle and white to show up against the color of metalthree
  • For the p doped region, I have told the node [midway,above] so that the text is in the middle of the picture and at the bottom. Notice how midway does not place the text at the true center of custom shapes. It only knows to place it relative to the previous line.
  • For the n doped regions, I did not want the text to sit relative to the line, I wanted it to be in the center of the shape. Thus, I told the node to be at a certain set of coordinates which I calculated to be the center of that shape, and set [align=center].
  • For the oxide layer, I wanted the text to show up against the oddly colored bricks. Therefore, I used [pos=.5,font=\bf\Large]. The “pos=.5” argument is functionally the same as “midway”, but offers greater freedom to customize. The font arguments tell the node to use text in boldface with a Large size.

The image ends up looking like this:

Placement and Style

Labels on Arrows

I’ve decided that I want to label the metal connections on our MOSFET, but I don’t want to place the text directly over the shape. Instead, I want to tell TikZ to draw little arrows pointing to what is labeled. This is easy. We just draw a line, which we tell to have an arrowhead, from a point to another point. At the first point, we tell it to have a label. I have used:

\draw [->] (1,5) node [above] {Source} -- (2.125,3.5);
		\draw [->] (10,5) node [above] {Drain} -- (8.975,3.5);
		\draw [->] (5.5,5) node [above] {Gate} -- (5.5,4.5);

Which when implemented, looks like this:

Animation with Beamer

Did you know that the same person that wrote TikZ wrote Beamer, the LaTeX slideshow creator? It’s true. This makes things quite convenient, as the author has designed it such that it is easy to integrate slide animations into your TikZ code.

For the final part of our MOSFET in TikZ, I’m going to add some animation. I want to make it obvious to the viewer how my MOSFET works going from the off state to saturation mode. I will do this by adding nodes to present the voltage relationship of each state on the screen, then pop up an image of the electron rich areas of the MOSFET. This is very easy to do with \only. Check out the final code below:

\documentclass{beamer}

\usepackage{tikz}
	\usetikzlibrary{patterns}

\title{\LaTeX~Surface Science and Electronics}
\author{Wesley T. Honeycutt}
\date{\today}

\newcommand{\metalone}{[pattern= horizontal lines, pattern color=blue]}
\newcommand{\metaltwo}{[pattern= vertical lines, pattern color=purple]}
\newcommand{\poly}{[pattern= grid, pattern color=red]}
\newcommand{\pdiff}{[pattern= north east lines, pattern color=orange]}
\newcommand{\ndiff}{[pattern= north west lines, pattern color=green]}
\newcommand{\pwell}{[pattern= crosshatch dots, pattern color=orange]}
\newcommand{\nwell}{[pattern= crosshatch dots, pattern color=green]}
\newcommand{\oxide}{[pattern = bricks, pattern color = olive]}
\newcommand{\silicon}{[fill = white]}
\newcommand{\metalthree}{[fill = teal]}

\begin{document}

	\frame{\titlepage}
	
	\frame{\frametitle{MOSFET}
		% General n-type mosfet
		\begin{tikzpicture}
		\draw \pdiff (0,.25) -- (0,3) -- (1,3) -- (1,2.5) to [out=270,in=180] (1.5,2) -- (3.75,2) to [out=0,in=270] (4.25,2.5) -- (4.25,3) -- (6.75,3) -- (6.75,2.5) to [out=270,in=180] (7.25,2) -- (9.5,2) to [out=0,in=270] (10,2.5) -- (10,3) -- (11,3) -- (11,.25) -- (0,.25) node [midway,above] {p doped Si};
		\draw \metalthree (0,0) rectangle (11,.25) node [midway, color=white]
		 {Si Substrate};
		\draw \oxide (4,3) rectangle (7,4) node [pos=.5,font=\bf\Large] {oxide};
		\draw \metalone (4,4) rectangle (7,4.5);
		\draw \ndiff (4.25,3) -- (1,3) -- (1,2.5) to [out=270,in=180] (1.5,2) -- (3.75,2) to [out=0,in=270] (4.25,2.5) -- (4.25,3) node at (2.625,2.5) [align=center] {n-type};
		\draw \ndiff (10,3) -- (6.75,3) -- (6.75,2.5) to [out=270,in=180] (7.25,2) -- (9.5,2) to [out=0,in=270] (10,2.5) -- (10,3) node at (8.375,2.5) [align=center] {n-type};
		\draw \metalone (1.25,3) rectangle (3,3.5);
		\draw \metalone (8,3) rectangle (9.75,3.5);
		\draw [->] (1,5) node [above] {Source} -- (2.125,3.5);
		\draw [->] (10,5) node [above] {Drain} -- (8.975,3.5);
		\draw [->] (5.5,5) node [above] {Gate} -- (5.5,4.5);
		\only<1> {\node at (5.5,-.5) [align=center] {$V_{GS} < V_{threshold}$};}
		\only<2-3> {\node at (5.5,-.5) [align=center] {$V_{GS} \geq V_{threshold}$};
			\node at (5.5,-1) [align=center] {$V_{DS} < V_{GS} - V_{threshold}$};
			}
		\only<3> {\draw [fill=white] (4.25,3) rectangle (6.75,2.5);
			\draw \ndiff (4.25,3) rectangle (6.75,2.5);
			}
		\only<4-5> {\node at (5.5,-.5) [align=center] {$V_{GS} \geq V_{threshold}$};
			\node at (5.5,-1) [align=center] {$V_{DS} = V_{GS} - V_{threshold}$};
			}
		\only<5> {\draw [fill=orange,orange] (4.25,3) rectangle (6.75,2.5);
			\draw [fill=white] (4.25,3) -- (4.25,2.65) -- (6.75,3) -- (4.75,3);
			\draw \ndiff (4.25,3) -- (4.25,2.65) -- (6.75,3) -- (4.75,3);
			}
		\only<6-7> {\node at (5.5,-.5) [align=center] {$V_{GS} \geq V_{threshold}$};
			\node at (5.5,-1) [align=center] {$V_{DS} > V_{GS} - V_{threshold}$};
			}
		\only<7> {\draw [fill=orange,orange] (4.25,3) rectangle (6.75,2.5);
			\draw [fill=white] (4.25,3) -- (4.25,2.85) -- (6.75,3) -- (4.75,3);
			\draw \ndiff (4.25,3) -- (4.25,2.85) -- (6.75,3) -- (4.75,3);
			}
		\end{tikzpicture}
	}
	
\end{document}

Each time I add an \only, I put slide numbers in pointed braces. The code between the curly braces will “only” show up on the slides listed in the pointed braces. The result of this code is shown in the following gif:

Animated

Wrap Up

I know that creating a MOSFET in TikZ is a bit specific. Still, I hope that this little tutorial gives everyone a feel for how to take make nice scale-able images in LaTeX using TikZ.

LaTeX: Drawing MOSFET in TikZ

I’m a big fan of using LaTeX for my scientific writing.  (What is LaTeX? It is a typesetting programming language that gives you much more flexibility than other writing environments.  wikipedia)  Since I have some time on my hands, I wanted to prepare for future presentations by writing up some notes and slides using in LaTeX for future use.  This includes drawing diagrams using TikZ.  This post describes how to draw a simple, generalized MOSFET in TikZ while standardizing some of the layer notation.

Setting up the Beamer environment

Before we get started with our drawing, let’s first set up a simple LaTeX environment.  Let’s say we want to make some slides for a lecture.  We can use the Beamer class in LaTeX to make these slides.  We tell LaTeX what we what to do.

\documentclass{beamer}

\begin{document}

\end{document}

Now, we add some title information into the preamble of the code, and we tell the document to produce a title slide.

\documentclass{beamer}

\title{Dr. Honeycutt's \LaTeX Surface Science and Electronics}
\author{Wesley T. Honeycutt}
\date{\today}

\begin{document}

	\frame{\titlepage}

\end{document}

The “\frame” command tells the LaTeX compiler to produce a single slide with the content in the curly braces. For our title slide, we want the content to be the information title information we included in the preamble. After compiling, it should look like this:

Title Slide

If you want to make your slides look fancy, there are plenty of things you can do. For this demonstration, we are only need a simple framework for the TikZ drawing, so we will just leave it at the default.

Drawing the MOSFET in TikZ

Now we are going to make a new slide with our drawing. We tell LaTeX that we will be using TikZ in the preamble. Then, we start a new slide (“\frame”) and begin our drawing. If you don’t know what a MOSFET is, or you just need a bit of a refresher, check out this for reference. Here is what my code looks like:

\documentclass{beamer}

\usepackage{tikz}

\title{\LaTeX~Surface Science and Electronics}
\author{Wesley T. Honeycutt}
\date{\today}

\begin{document}

	\frame{\titlepage}
	
	\frame{\frametitle{MOSFET}
		% General n-type mosfet
		\begin{tikzpicture}
		\draw (0,.25) -- (0,3) -- (1,3) -- (1,2.5) to [out=270,in=180] (1.5,2) -- (3.75,2) to [out=0,in=270] (4.25,2.5) -- (4.25,3) -- (6.75,3) -- (6.75,2.5) to [out=270,in=180] (7.25,2) -- (9.5,2) to [out=0,in=270] (10,2.5) -- (10,3) -- (11,3) -- (11,.25) -- (0,.25);
		\draw (0,0) rectangle (11,.25);
		\draw (4,3) rectangle (7,4);
		\draw (4,4) rectangle (7,4.5);
		\draw (4.25,3) -- (1,3) -- (1,2.5) to [out=270,in=180] (1.5,2) -- (3.75,2) to [out=0,in=270] (4.25,2.5) -- (4.25,3);
		\draw (10,3) -- (6.75,3) -- (6.75,2.5) to [out=270,in=180] (7.25,2) -- (9.5,2) to [out=0,in=270] (10,2.5) -- (10,3);
		\draw (1.25,3) rectangle (3,3.5);
		\draw (8,3) rectangle (9.75,3.5);
		\end{tikzpicture}
	}

\end{document}

In the preamble, I have told LaTeX I will be using the TikZ package. After the title slide, I added a new “\frame” and gave it a “\frametitle”. Note how the curly brace of the “\frame” does not close until line 25. In this “\frame” I have started a tikzpicture environment. This tells LaTeX that it should start using the TikZ code in this section. I have two types of drawings here. The first are simple rectangles. These rectangles are bounded by the opposing corners in (x,y) coordinates. The default units here are cm. The second type of drawing is a complex line shape. The code tells TikZ that I want a line “–” drawn from one (x,y) coordinate to a second coordinate. Multiples of these lines can be drawn in a single line. I have drawn curved lines with a different notation. I tell TikZ to draw from the first (x,y) coordinate “to [out=a,in=b]” where “a” and “b” are angles. This creates a curved line which connects to the previous and next segment at the defined angles. There are many ways to draw curves in TikZ, but for simple figures such as depicted here, this approach is sufficient. Finally, note how each line of the “tikzpicture” code is ended by a semicolon. This line ending is not something that you normally see in LaTeX, so be sure you don’t forget it.

When I compile my code, the slide with the drawing of the MOSFET in TikZ looks like this:

Drawing of MOSFET in TikZ

Adding some color

Now let’s add some color to our image. Using TikZ, adding a color is as easy as mentioning a fill color. But this is a special case. When drawing electronic components at the surface level, there are standard colors used for certain things. The standardized colors make it easy for Engineers to understand how a circuit works at a glance. These colors, from the classic VLSI design program “Magic”, are show in the picture (from Prof. Stine’s guide to Magic) below:

Standard VLSI colors

I want to use these colors for all of the drawings in my slides and notes. Therefore, I am going to make a new command for the colors in LaTeX. Additionally, since I expect my drawings to overlap at times, I want to give the colors patterns as well. I add the following code to my preamble:

\newcommand{\metalone}{[pattern= horizontal lines, pattern color=blue]}
\newcommand{\metaltwo}{[pattern= vertical lines, pattern color=purple]}
\newcommand{\poly}{[pattern= grid, pattern color=red]}
\newcommand{\pdiff}{[pattern= north east lines, pattern color=orange]}
\newcommand{\ndiff}{[pattern= north west lines, pattern color=green]}
\newcommand{\pwell}{[pattern= crosshatch dots, pattern color=orange]}
\newcommand{\nwell}{[pattern= crosshatch dots, pattern color=green]}
\newcommand{\oxide}{[pattern = bricks, pattern color = olive]}
\newcommand{\silicon}{[fill = white]}
\newcommand{\metalthree}{[fill = teal]}

In this section, I am defining a new custom command for LaTeX with the command name in the first set of curly braces, and the action to be performed in the second set of curly braces. The actions include a pattern and a pattern color in a format acceptable to TikZ notation. All I have to do is include the command in my drawing for the color and pattern to apply. If I decide to change a color later on (maybe metalthree needs to be pink instead of teal), all I have to do is change the command in one location and every instance of the command in the code is changed.

Additionally, since we decided to use patterns with the color fill commands, we need to add a line in the preamble declaring that we are going to use patterns. This is the case for all optional TikZ libraries we use in the future.

When we take a look at the complete code for the MOSFET in TikZ slide, it should look like this:

\documentclass{beamer}

\usepackage{tikz}
	\usetikzlibrary{patterns}

\title{\LaTeX~Surface Science and Electronics}
\author{Wesley T. Honeycutt}
\date{\today}

\newcommand{\metalone}{[pattern= horizontal lines, pattern color=blue]}
\newcommand{\metaltwo}{[pattern= vertical lines, pattern color=purple]}
\newcommand{\poly}{[pattern= grid, pattern color=red]}
\newcommand{\pdiff}{[pattern= north east lines, pattern color=orange]}
\newcommand{\ndiff}{[pattern= north west lines, pattern color=green]}
\newcommand{\pwell}{[pattern= crosshatch dots, pattern color=orange]}
\newcommand{\nwell}{[pattern= crosshatch dots, pattern color=green]}
\newcommand{\oxide}{[pattern = bricks, pattern color = olive]}
\newcommand{\silicon}{[fill = white]}
\newcommand{\metalthree}{[fill = teal]}

\begin{document}

	\frame{\titlepage}
	
	\frame{\frametitle{MOSFET}
		% General n-type mosfet
		\begin{tikzpicture}
		\draw \pdiff (0,.25) -- (0,3) -- (1,3) -- (1,2.5) to [out=270,in=180] (1.5,2) -- (3.75,2) to [out=0,in=270] (4.25,2.5) -- (4.25,3) -- (6.75,3) -- (6.75,2.5) to [out=270,in=180] (7.25,2) -- (9.5,2) to [out=0,in=270] (10,2.5) -- (10,3) -- (11,3) -- (11,.25) -- (0,.25);
		\draw \metalthree (0,0) rectangle (11,.25);
		\draw \oxide (4,3) rectangle (7,4);
		\draw \metalone (4,4) rectangle (7,4.5);
		\draw \ndiff (4.25,3) -- (1,3) -- (1,2.5) to [out=270,in=180] (1.5,2) -- (3.75,2) to [out=0,in=270] (4.25,2.5) -- (4.25,3);
		\draw \ndiff (10,3) -- (6.75,3) -- (6.75,2.5) to [out=270,in=180] (7.25,2) -- (9.5,2) to [out=0,in=270] (10,2.5) -- (10,3);
		\draw \metalone (1.25,3) rectangle (3,3.5);
		\draw \metalone (8,3) rectangle (9.75,3.5);
		\end{tikzpicture}
	}

\end{document}

Compiling this code will give us this as our second slide:

Color Pattern Filled MOSFET in TikZ

Witch1

In early 2014, I was inspired to make some mask art.  The final piece has no proper name, but I refer to it when speaking to others as “The Witch Mask”.  Work on the mask was undertaken over several months, finally completed in October 2014.  This post and the related follow up posts will detail the creation of this mask from concept to reality.

Inspiration 1 – Israeli Stone Mask

The original inspiration for the creation of the witch mask came from two sources.  First, was an article on the world’s oldest masks going on display in Jerusalem.  An article in National Geographic goes over the exhibit.  One of the masks in particular caught my eye as something creepy and unnatural.   Among the finds recovered from Nahal Hamar is this Neolithic stone mask:

Israeli Neolithic stone mask ca. 7,000 BCE

It is reported to be ~9,000 years old.

This unnamed piece was discovered in the vicinity of Horvat Duma by a farmer.  The journey from field to find is slightly unpleasant as well.  According to the story, the mask was purchased from the farmer who discovered it by Israeli general Moshe Dayan.  However, Gen. Dayan was not the nicest guy.  While he fancied himself an archaeologist, he acquired much of his collection through shady means.  An article by Raz Kletter (see § 4.3) pulls quotes from the various memoirs of Gen. Dayan relating how he did not actually purchase the mask, he just paid the driver to take him there.

The emptiness of the mask’s expression and the sordid tale to accompany it makes for some interesting inspiration.  But it took a second source to produce my idea.

Inspiration 2 – Witch

The image below is a digital painting I found while browsing around Reddit.  The work as I saw it had no source to accompany it at the time, but it struck a chord with me.  The empty expression, the facial features, and the darkness produced a connection to the Israeli mask.  Even if they weren’t related by, there was a certain kinship to them.  At that point I was inspired to create.

"Witch" by Maaria Laurinen

With post facto research, I have discovered that the illustration is entitled “Witch”, appropriately enough.  It was published to DeviantArt around 2008 or 2009 by Maaria Laurinen.  You can view more of her work here and here.

The First Layers

The witch mask was started with an oval ring cut from matboard.  The oval hole in the center had an opening with an approximate size to fit my face.  Using matboard gave me a flat surface to start building up the contour.

The face was produced in a layered process using a paper mache variant I enjoy using.  I create this using shreds of old printouts from the lab.  The first step is to grind the paper with water in a blender to produce a slurry.  Then I press out the water using cheesecloth.  The still wet paper mash is mixed with white glue (polyvinyl acetate) and plaster of paris (anhydrous calcium sulfate).  The glue gives helps bind the paper shreds together, and the plaster provides weight and strength.  The final texture of the material is like an old fashioned plaster cast.  It makes for a nice stone-like feel.

First Layers of the witch mask

A side view of the first two layers.

For the start of the witch mask, I did domed shape with a nose on the first layer.  Each layer, after drying for several days, is coated with matte surface Mod Podge or sealant to keep the things together.  In this case, drying the first layer was accelerated by placing it in an oven.  Use of the oven degrades the PVA white glue, causing the slight browning of the first layer shown above.  The matte surface is important, as it lends greater surface area for future layers or paints to bond to.  Pictures above depict the front and side view of the mask after the inital domed/nose layer, Mod Podge, and the start of the second layer.

After everything was dried and coated, I tested the fit of the mask for the first time.

A blank slate.

To be continued…